AMX DESIGN XPRESS V 1.5 - PROGRAMMER GUIDE User's Guide Page 98
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98 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block
UG197 (v1.5) July 22, 2009
Appendix A: Integrated Endpoint Block Attributes
R
ACTIVELANESIN
8-bit Hex Bit mask of available active lanes. Valid settings are:
01h:x1
03h:x2
0Fh:x4
FFh:x8
TXTSNFTS
Integer Sets the number of FTS sequences generally
advertised in the TS1 Ordered Sets (used for all
lanes).
TXTSNFTSCOMCLK
Integer Sets the number of FTS sequences advertised in the
TS1 Ordered Sets when the Link Configuration
register shows that a common clock source is
selected (used for all lanes).
RETRYRAMREADLATENCY
Integer Specifies the Retry buffer read latency. Valid range is
2..6.
RETRYRAMWRITELATENCY
Integer Specifies the Retry buffer write latency. Valid
settings are 1 or 2.
RETRYRAMSIZE
12-bit Hex Specifies width of Retry buffer address.
INFINITECOMPLETIONS
Boolean FALSE specifies the block does not advertise infinite
completion credits. TRUE specifies the block does
advertise infinite completion flow control credits.
Must be set to TRUE.
TLRAMREADLATENCY
Integer Specifies the read latency for the TX and RX buffers
in terms of cycles of core_clk for TX or user_clk for
RX. Valid range is 2 .. 6.
TLRAMWRITELATENCY
Integer Specifies the write latency for TX and RX buffers in
terms of cycles of user_clk for TX or core_clk for RX.
Valid settings are 1 or 2.
L0SEXITLATENCY
Integer Sets the exit latency from the L0s state to be applied
where separate clocks are used. Transferred to the
Link Capabilities register. Possible values are:
0: less than 64 ns
1: 64 ns to less than 128 ns
2: 128 ns to less than 256 ns
3: 256 ns to less than 512 ns
4: 512 ns to less than 1 µs
5: 1 µs to less than 2 µs
6: 2 µs to 4 µs
7: more than 4 µs
Table A-7: Integrated Endpoint Block Attributes (Continued)
Attribute Name Type Description
- Virtex-5 FPGA 1
- Integrated Endpoint Block 1
- Revision History 3
- VC1*, LOWPRIORITYVCCOUNT 4
- Table of Contents 5
- About This Guide 9
- Additional Documentation 10
- Additional Support Resources 11
- Typographical Conventions 11
- Preface: About This Guide 12
- Block Overview 13
- Memory Requirements 15
- Use Models 15
- Chapter 2 17
- Transaction Layer 18
- Data Link Layer 19
- Physical Layer 19
- Physical Layer Lane Module 20
- Clock Frequency 21
- Integrated 22
- Endpoint Block 22
- Transmit 28
- Channels 29
- Channel Ready 29
- Channel Select 29
- Transmit Framing 29
- Framing Errors 30
- DWORD Enables 30
- Transmit Handshake 30
- UG197_c2_04_030607 31
- Receive Framing 32
- Receive Handshake 32
- UG197_c2_06_111906 34
- Management Interface 37
- UG197_c2_08_082406 38
- Block RAM Interface 40
- RX and TX Buffer Capacity 41
- Retry Buffer Size 41
- Transceiver Interface 42
- Power Management Interface 45
- Registers 53
- Table 2-19: MSI Registers 55
- Reserved Registers 56
- Chapter 3 63
- Chapter 4 65
- Configuration Requests 66
- Transaction Ordering 67
- Interrupt Handling 68
- INTERRUPTDISABLE output: 69
- Error Detection 70
- Error Reporting 74
- Message Tags 76
- Phantom Function Support 76
- Lane Width 77
- Lane Reversal 77
- Workaround 78
- Appendix A 91
- TOTALCREDITS attributes are 92
- Initial Flow Control Credits 93
- Extended Capabilities 94
- The offset to the next PCI 105
- Contains the offset of 105
- UG197 (v1.5) July 22, 2009 108
- Glossary 109
- Function 112
- Hot plug 112
- Hot swap 112
- Isochronous data transfer 112
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