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Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 103
UG197 (v1.5) July 22, 2009
Integrated Endpoint Block Attributes
R
PMCAPABILITYDSI
Boolean Device Specific Initialization (DSI).
TRUE: 1
FALSE: 0
Transferred to the PM Capabilities register.
PMCAPABILITYAUXCURRENT
3-bit Hex Reserved. Must be set to 0h.
PMCAPABILITYD1SUPPORT
Boolean D1 Support. Transferred to the PM Capabilities
register.
Must be set to FALSE.
PMCAPABILITYD2SUPPORT
Boolean D2 Support. Transferred to the PM Capabilities
register.
Must be set to FALSE.
PMCAPABILITYPMESUPPORT
5-bit Hex PME Support. These five bits indicate support for
PME generation within D3
COLD
, D3
HOT
, D2, D1,
and D0, respectively. Transferred to the PM
Capabilities register.
Must be set to 0h.
PMDATA0
8-bit Hex Reserved. Must be set to 0h.
PMDATA1
8-bit Hex Reserved. Must be set to 0h.
PMDATA2
8-bit Hex Reserved. Must be set to 0h.
PMDATA3
8-bit Hex Reserved. Must be set to 0h.
PMDATA4
8-bit Hex Reserved. Must be set to 0h.
PMDATA5
8-bit Hex Reserved. Must be set to 0h.
PMDATA6
8-bit Hex Reserved. Must be set to 0h.
PMDATA7
8-bit Hex Reserved. Must be set to 0h.
PMDATASCALE0
Integer Reserved. Must be set to 0.
PMDATASCALE1
Integer Reserved. Must be set to 0.
PMDATASCALE2
Integer Reserved. Must be set to 0.
PMDATASCALE3
Integer Reserved. Must be set to 0.
PMDATASCALE4
Integer Reserved. Must be set to 0.
PMDATASCALE5
Integer Reserved. Must be set to 0.
PMDATASCALE6
Integer Reserved. Must be set to 0.
PMDATASCALE7
Integer Reserved. Must be set to 0.
PMDATASCALE8
Integer Reserved. Must be set to 0.
MSICAPABILITYNEXTPTR
8-bit Hex Pointer to the next item in the capabilities list or 00h
if no further capability structures are available at
higher addresses.
Table A-7: Integrated Endpoint Block Attributes (Continued)
Attribute Name Type Description
- Virtex-5 FPGA 1
- Integrated Endpoint Block 1
- Revision History 3
- VC1*, LOWPRIORITYVCCOUNT 4
- Table of Contents 5
- About This Guide 9
- Additional Documentation 10
- Additional Support Resources 11
- Typographical Conventions 11
- Preface: About This Guide 12
- Block Overview 13
- Memory Requirements 15
- Use Models 15
- Chapter 2 17
- Transaction Layer 18
- Data Link Layer 19
- Physical Layer 19
- Physical Layer Lane Module 20
- Clock Frequency 21
- Integrated 22
- Endpoint Block 22
- Transmit 28
- Channels 29
- Channel Ready 29
- Channel Select 29
- Transmit Framing 29
- Framing Errors 30
- DWORD Enables 30
- Transmit Handshake 30
- UG197_c2_04_030607 31
- Receive Framing 32
- Receive Handshake 32
- UG197_c2_06_111906 34
- Management Interface 37
- UG197_c2_08_082406 38
- Block RAM Interface 40
- RX and TX Buffer Capacity 41
- Retry Buffer Size 41
- Transceiver Interface 42
- Power Management Interface 45
- Registers 53
- Table 2-19: MSI Registers 55
- Reserved Registers 56
- Chapter 3 63
- Chapter 4 65
- Configuration Requests 66
- Transaction Ordering 67
- Interrupt Handling 68
- INTERRUPTDISABLE output: 69
- Error Detection 70
- Error Reporting 74
- Message Tags 76
- Phantom Function Support 76
- Lane Width 77
- Lane Reversal 77
- Workaround 78
- Appendix A 91
- TOTALCREDITS attributes are 92
- Initial Flow Control Credits 93
- Extended Capabilities 94
- The offset to the next PCI 105
- Contains the offset of 105
- UG197 (v1.5) July 22, 2009 108
- Glossary 109
- Function 112
- Hot plug 112
- Hot swap 112
- Isochronous data transfer 112
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