AMX DESIGN XPRESS V 1.5 - PROGRAMMER GUIDE User's Guide Page 31

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Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 31
UG197 (v1.5) July 22, 2009
Virtex-5 FPGA Integrated Endpoint Block Interface Descriptions
After transmission of a packet, a subsequent packet on the same channel (FIFO and TC)
can be sent immediately. For packets on a different channel (FIFO or TC), the user logic
must pause until
LLKTXDSTRDYN is asserted for two cycles after LLKTXEOFN before
changing the
LLKTXCHFIFO or LLKTXCHTC signal.
If the transmit buffer becomes full during packet transfer, it deasserts
LLKTXDSTRDYN and
stalls data transfers on the Transaction Layer interface until space becomes available again
as the packet is sent over the serial interface. The user can optionally check the amount of
space in a channel using
LLKTXCHANSPACE and decide to not begin sending the packet
over the Transaction Layer interface if insufficient space is available to send the packet
without stalling. The requirement on channel switching timing as shown in Figure 2-6
must also be observed.
LLKTXENABLEN is ignored unless LLKTXSRCRDYN and LLKTXDSTRDYN are asserted.
Receive
The receive portion of the interface passes the data received from the link partner to the
user application in fabric.
Figure 2-6: Transaction Layer Interface Transmit Channel Switching Timing Diagram
CRMUSERCLK
LLKTXCHFIFO
LLKTXCHTC
LLKTXSOFN
LLKTXEOFN
LLKTXSRCRDYN
LLKTXDSTRDYN
LLKTXDATA
LLKTXENABLEN
H0 H1 H0 H1H2 D0
11 11
0 2 (CPL)
0
0 (P)
64
1100 00 00 00 00 00 00 00 01
H2 D0D1 D2 D1 D2D3 D4 D3 XXD5 D6
Note: Need to wait an additional two cycles of
LLKTXDSTRDYN assertion after LLKTXEOFN
before switching LLKTXCHFIFO or LLKTXCHTC.
UG197_c2_04_030607
H0 H1 H2 D1
00 00
LLKTXCHANSPACE[7:0]
nP nC-1 nP-2nC nC-2
nP nP-1
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