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96 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block
UG197 (v1.5) July 22, 2009
Appendix A: Integrated Endpoint Block Attributes
R
Integrated Endpoint Block Attributes
Table A-7 summarizes the integrated Endpoint block attributes.
Table A-7: Integrated Endpoint Block Attributes
Attribute Name Type Description
VC0TXFIFOBASEP
13-bit Hex Base of address area used for header and data of
transmitted posted packets associated with VC0.
Must be set to 0.
VC0TXFIFOBASENP
13-bit Hex Base of address area used for header and data of
transmitted non-posted packets associated with
VC0.
VC0TXFIFOBASEC
13-bit Hex Base of address area used for header and data of
transmitted completion packets associated with
VC0.
VC0TXFIFOLIMITP
13-bit Hex Top of address area used for header and data of
transmitted posted packets associated with VC0.
The maximum allowed FIFO size is 32,768 bytes.
VC0TXFIFOLIMITNP
13-bit Hex Top of address area used for header and data of
transmitted non-posted packets associated with
VC0. The maximum allowed FIFO size is 512 bytes.
VC0TXFIFOLIMITC
13-bit Hex Top of address area used for header and data of
transmitted completion packets associated with
VC0. The maximum allowed FIFO size is 32,768
bytes.
VC0TOTALCREDITSPH
7-bit Hex Number of credits that should be advertised for
posted headers received on VC0. Can be limited by
the FIFO size. The maximum supported value is 8.
VC0TOTALCREDITSNPH
7-bit Hex Number of credits that should be advertised for
non-posted headers received on VC0. Can be
limited by the FIFO size. The maximum supported
value is 8. There is no corresponding
VC0TOTALCREDITSNPD attribute as this is always
advertised as infinite.
VC0TOTALCREDITSCH
7-bit Hex Number of credits that should be advertised for
completion headers received on VC0. Can be
limited by the FIFO size. The maximum supported
value is 8. Must be set to 0 when
INFINITECOMPLETIONS = TRUE.
VC0TOTALCREDITSPD
11-bit Hex Number of credits that should be advertised for
posted data received on VC0. Limited by the FIFO
size and/or the overriding maximum of 8 posted
data packets that can be buffered on VC0.
VC0TOTALCREDITSCD
11-bit Hex Number of credits that should be advertised for
Completion data received on VC0. Limited by the
FIFO size and/or the overriding maximum of 8
completion data packets that can be buffered on
VC0. Must be set to 0 when
INFINITECOMPLETIONS
= TRUE.
- Virtex-5 FPGA 1
- Integrated Endpoint Block 1
- Revision History 3
- VC1*, LOWPRIORITYVCCOUNT 4
- Table of Contents 5
- About This Guide 9
- Additional Documentation 10
- Additional Support Resources 11
- Typographical Conventions 11
- Preface: About This Guide 12
- Block Overview 13
- Memory Requirements 15
- Use Models 15
- Chapter 2 17
- Transaction Layer 18
- Data Link Layer 19
- Physical Layer 19
- Physical Layer Lane Module 20
- Clock Frequency 21
- Integrated 22
- Endpoint Block 22
- Transmit 28
- Channels 29
- Channel Ready 29
- Channel Select 29
- Transmit Framing 29
- Framing Errors 30
- DWORD Enables 30
- Transmit Handshake 30
- UG197_c2_04_030607 31
- Receive Framing 32
- Receive Handshake 32
- UG197_c2_06_111906 34
- Management Interface 37
- UG197_c2_08_082406 38
- Block RAM Interface 40
- RX and TX Buffer Capacity 41
- Retry Buffer Size 41
- Transceiver Interface 42
- Power Management Interface 45
- Registers 53
- Table 2-19: MSI Registers 55
- Reserved Registers 56
- Chapter 3 63
- Chapter 4 65
- Configuration Requests 66
- Transaction Ordering 67
- Interrupt Handling 68
- INTERRUPTDISABLE output: 69
- Error Detection 70
- Error Reporting 74
- Message Tags 76
- Phantom Function Support 76
- Lane Width 77
- Lane Reversal 77
- Workaround 78
- Appendix A 91
- TOTALCREDITS attributes are 92
- Initial Flow Control Credits 93
- Extended Capabilities 94
- The offset to the next PCI 105
- Contains the offset of 105
- UG197 (v1.5) July 22, 2009 108
- Glossary 109
- Function 112
- Hot plug 112
- Hot swap 112
- Isochronous data transfer 112
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