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42 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block
UG197 (v1.5) July 22, 2009
Chapter 2: Integrated Endpoint Block Functionality
R
Ports
Table 2-11, Table 2-12, and Table 2-13 define the transmit buffer, receive buffer, and retry
buffer ports for the Block RAM interface, respectively.
Transceiver Interface
Connections between the Transceiver Interface and the RocketIO transceivers are included
in the CORE Generator wrappers. There are eight copies of each of the signals in
Table 2-14, one for each lane (n = 0 .. 7). If less than eight lanes are used, the lower
numbered lanes should be connected to RocketIO transceivers, starting with lane 0, and
the unused input signals should be tied off as indicated. There are two copies of each of the
Table 2-11: Transmit Buffer Ports
Port Direction
Clock
Domain
Description
MIMTXBWDATA[63:0]
Output user_clk TX Buffer Write data
MIMTXBWADD[12:0]
Output user_clk TX Buffer Write address
MIMTXBRADD[12:0]
Output core_clk TX Buffer Read address
MIMTXBWEN
Output user_clk TX Buffer Write enable
MIMTXBRDATA[63:0]
Input core_clk TX Buffer Read data
MIMTXBREN
Output core_clk TX Buffer Read enable
Table 2-12: Receive Buffer Ports
Port Direction
Clock
Domain
Description
MIMRXBWDATA[63:0]
Output core_clk RX Buffer Write data
MIMRXBWADD[12:0]
Output core_clk RX Buffer Write address
MIMRXBRADD[12:0]
Output user_clk RX Buffer Read address
MIMRXBWEN
Output core_clk RX Buffer Write enable
MIMRXBRDATA[63:0]
Input user_clk RX Buffer Read data
MIMRXBREN
Output user_clk RX Buffer Read enable
Table 2-13: Retry Buffer Ports
Port Direction
Clock
Domain
Description
MIMDLLBWDATA[63:0]
Output core_clk DLL Retry buffer Write data
MIMDLLBWADD[11:0]
Output core_clk DLL Retry buffer Write address
MIMDLLBRADD[11:0]
Output core_clk DLL Retry buffer Read address
MIMDLLBWEN
Output core_clk DLL Retry buffer Write enable
MIMDLLBRDATA[63:0]
Input core_clk DLL Retry buffer Read data
MIMDLLBREN
Output core_clk DLL Retry buffer Read enable
- Virtex-5 FPGA 1
- Integrated Endpoint Block 1
- Revision History 3
- VC1*, LOWPRIORITYVCCOUNT 4
- Table of Contents 5
- About This Guide 9
- Additional Documentation 10
- Additional Support Resources 11
- Typographical Conventions 11
- Preface: About This Guide 12
- Block Overview 13
- Memory Requirements 15
- Use Models 15
- Chapter 2 17
- Transaction Layer 18
- Data Link Layer 19
- Physical Layer 19
- Physical Layer Lane Module 20
- Clock Frequency 21
- Integrated 22
- Endpoint Block 22
- Transmit 28
- Channels 29
- Channel Ready 29
- Channel Select 29
- Transmit Framing 29
- Framing Errors 30
- DWORD Enables 30
- Transmit Handshake 30
- UG197_c2_04_030607 31
- Receive Framing 32
- Receive Handshake 32
- UG197_c2_06_111906 34
- Management Interface 37
- UG197_c2_08_082406 38
- Block RAM Interface 40
- RX and TX Buffer Capacity 41
- Retry Buffer Size 41
- Transceiver Interface 42
- Power Management Interface 45
- Registers 53
- Table 2-19: MSI Registers 55
- Reserved Registers 56
- Chapter 3 63
- Chapter 4 65
- Configuration Requests 66
- Transaction Ordering 67
- Interrupt Handling 68
- INTERRUPTDISABLE output: 69
- Error Detection 70
- Error Reporting 74
- Message Tags 76
- Phantom Function Support 76
- Lane Width 77
- Lane Reversal 77
- Workaround 78
- Appendix A 91
- TOTALCREDITS attributes are 92
- Initial Flow Control Credits 93
- Extended Capabilities 94
- The offset to the next PCI 105
- Contains the offset of 105
- UG197 (v1.5) July 22, 2009 108
- Glossary 109
- Function 112
- Hot plug 112
- Hot swap 112
- Isochronous data transfer 112
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