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Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 97
UG197 (v1.5) July 22, 2009
Integrated Endpoint Block Attributes
R
VC0RXFIFOBASEP
13-bit Hex Base of address area used for header and data of
received posted packets associated with VC0. Must
be set to 0.
VC0RXFIFOBASENP
13-bit Hex Base of address area used for header and data of
received non-posted packets associated with VC0.
VC0RXFIFOBASEC
13-bit Hex Base of address area used for header and data of
received completion packets associated with VC0.
VC0RXFIFOLIMITP
13-bit Hex Top of address area used for header and data of
received posted packets associated with VC0. The
maximum allowed FIFO size is 32,768 bytes.
VC0RXFIFOLIMITNP
13-bit Hex Top of address area used for header and data of
received non-posted packets associated with VC0.
The maximum allowed FIFO size is 512 bytes.
VC0RXFIFOLIMITC
13-bit Hex Top of address area used for header and data of
received completion packets associated with VC0.
Must be set to
VC0RXFIFOLIMITNP + (216 + (9 *
XPMAXPAYLOAD)) / 8 -1 when the
INFINITECOMPLETIONS attribute is set to TRUE.
The maximum allowed FIFO size is 32,768 bytes.
VC1TXFIFOBASEP
13-bit Hex Reserved. Should be set to VC0TXFIFOLIMITC + 1.
VC1TXFIFOBASENP
13-bit Hex Reserved. Should be set to VC0TXFIFOLIMITC + 1.
VC1TXFIFOBASEC
13-bit Hex Reserved. Should be set to VC0TXFIFOLIMITC + 1.
VC1TXFIFOLIMITP
13-bit Hex Reserved. Should be set to VC0TXFIFOLIMITC.
VC1TXFIFOLIMITNP
13-bit Hex Reserved. Should be set to VC0TXFIFOLIMITC.
VC1TXFIFOLIMITC
13-bit Hex Reserved. Should be set to VC0TXFIFOLIMITC.
VC1TOTALCREDITSPH
7-bit Hex Reserved. Should be set to 00h.
VC1TOTALCREDITSNPH
7-bit Hex Reserved. Should be set to 00h.
VC1TOTALCREDITSCH
7-bit Hex Reserved. Should be set to 00h.
VC1TOTALCREDITSPD
11-bit Hex Reserved. Should be set to 000h.
VC1TOTALCREDITSCD
11-bit Hex Reserved. Should be set to 000h.
VC1RXFIFOBASEP
13-bit Hex Reserved. Should be set to VC0RXFIFOLIMITC + 1.
VC1RXFIFOBASENP
13-bit Hex Reserved. Should be set to VC0RXFIFOLIMITC + 1.
VC1RXFIFOBASEC
13-bit Hex Reserved. Should be set to VC0RXFIFOLIMITC + 1.
VC1RXFIFOLIMITP
13-bit Hex Reserved. Should be set to VC0RXFIFOLIMITC.
VC1RXFIFOLIMITNP
13-bit Hex Reserved. Should be set to VC0RXFIFOLIMITC.
VC1RXFIFOLIMITC
13-bit Hex Reserved. Should be set to VC0RXFIFOLIMITC.
Table A-7: Integrated Endpoint Block Attributes (Continued)
Attribute Name Type Description
- Virtex-5 FPGA 1
- Integrated Endpoint Block 1
- Revision History 3
- VC1*, LOWPRIORITYVCCOUNT 4
- Table of Contents 5
- About This Guide 9
- Additional Documentation 10
- Additional Support Resources 11
- Typographical Conventions 11
- Preface: About This Guide 12
- Block Overview 13
- Memory Requirements 15
- Use Models 15
- Chapter 2 17
- Transaction Layer 18
- Data Link Layer 19
- Physical Layer 19
- Physical Layer Lane Module 20
- Clock Frequency 21
- Integrated 22
- Endpoint Block 22
- Transmit 28
- Channels 29
- Channel Ready 29
- Channel Select 29
- Transmit Framing 29
- Framing Errors 30
- DWORD Enables 30
- Transmit Handshake 30
- UG197_c2_04_030607 31
- Receive Framing 32
- Receive Handshake 32
- UG197_c2_06_111906 34
- Management Interface 37
- UG197_c2_08_082406 38
- Block RAM Interface 40
- RX and TX Buffer Capacity 41
- Retry Buffer Size 41
- Transceiver Interface 42
- Power Management Interface 45
- Registers 53
- Table 2-19: MSI Registers 55
- Reserved Registers 56
- Chapter 3 63
- Chapter 4 65
- Configuration Requests 66
- Transaction Ordering 67
- Interrupt Handling 68
- INTERRUPTDISABLE output: 69
- Error Detection 70
- Error Reporting 74
- Message Tags 76
- Phantom Function Support 76
- Lane Width 77
- Lane Reversal 77
- Workaround 78
- Appendix A 91
- TOTALCREDITS attributes are 92
- Initial Flow Control Credits 93
- Extended Capabilities 94
- The offset to the next PCI 105
- Contains the offset of 105
- UG197 (v1.5) July 22, 2009 108
- Glossary 109
- Function 112
- Hot plug 112
- Hot swap 112
- Isochronous data transfer 112
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