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Preface

About This Guide

This guide serves as a technical reference describing the Virtex®-5 FPGA Integrated

Endpoint Block for PCI Express® designs (integrated Endpoint block). Users intending to

implement the integrated Endpoint block should use the CORE Generator™ tool to create

the LogiCORE™ IP Endpoint Block Plus for PCI Express (Endpoint Block Plus wrapper).

The Endpoint Block Plus wrapper contains all the settings and interface logic needed to

create a compliant PCI Express design. See Chapter 3, “Designing with the Endpoint Block

Plus Wrapper,” for more information.

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, LogiCORE IP Endpoint Block Plus for PCI Express User Guide describes how to use the

Endpoint Block Plus wrapper to create an Endpoint design for PCI Express operation. The

LogiCORE IP Endpoint Block Plus for PCI Express User Guide should primarily be used when

creating a design with the integrated Endpoint block.

The Virtex-5 FPGA Integrated Endpoint Block for PCI Express Designs User Guide (this guide)

provides an in-depth description of the integrated Endpoint block's behavior. Even though

the Endpoint Block Plus wrapper extracts much of this behavior from the user, this guide

is useful as a companion document to the LogiCORE IP Endpoint Block Plus for PCI Express

User Guide to provide a better understanding of the integrated Endpoint block. Because

this user guide describes the integrated Endpoint block’s ports and attributes, it is

extremely helpful when debugging user designs. It also provides a list of known

restrictions to be referenced when encountering design problems.

Guide Contents

This guide contains the following chapters:

• Chapter 1, “Virtex-5 FPGA Integrated Endpoint Block Overview,”provides a brief

introduction to the integrated Endpoint block embedded in the Virtex-5 devices.

• Chapter 2, “Integrated Endpoint Block Functionality,” gives an architectural overview

of the block and detailed descriptions of each block interface.

• Chapter 3, “Designing with the Endpoint Block Plus Wrapper,” provides more

information on using the CORE Generator GUI to generate the appropriate

LogiCORE IP to implement the Virtex-5 FPGA Integrated Endpoint block in a PCI

Express design.

• Chapter 4, “Integrated Endpoint Block Operation,” provides in-depth information on

various design considerations.

• Chapter 5, “Simulating with the Integrated Endpoint Block,” introduces simulating

with the Virtex-5 FPGA Integrated Endpoint block.

• Appendix A, “Integrated Endpoint Block Attributes,” provides detailed information

on the attributes that can be set on the integrated Endpoint block. Because these

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