AMX DESIGN XPRESS V 1.5 - PROGRAMMER GUIDE User's Guide Page 30

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30 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block
UG197 (v1.5) July 22, 2009
Chapter 2: Integrated Endpoint Block Functionality
R
Framing Errors
The following conditions are framing errors and are not allowed:
Two
SOFs without an intervening EOF
Two EOFs without an intervening SOF
An SOF and EOF in the same cycle
DWORD Enables
The Transaction Layer interface data bus, LLKTXDATA, is 64 bits wide, allowing the user to
transfer one QWORD of data into the integrated Endpoint block per clock cycle. Because
the PCIe protocol allows DWORD (32-bit) alignment of header and data, certain QWORDs
contain only one valid DWORD. The
LLKTXENABLEN[1:0] bus indicates which DWORD(s)
contain valid header or data information. Bit 1 of
LLKTXENABLEN[1:0] refers to
LLKTXDATA[63:32], and bit 0 refers to LLKTXDATA[31:0]. A value of 0 indicates that the
corresponding DWORD is valid.
All 64 bits of
LLKTXDATA must be enabled, except on the last cycle of a TLP transfer, when
LLKTXEOFN = 0. For the last QWORD of a packet, it is possible that only LLKTXDATA[63:32]
is valid because of DWORD alignment. This is denoted by
LLKTXENABLEN[1:0] = 01 during
LLKTXEOFN. Otherwise, LLKTXENABLEN[1:0] = 00 is used for all other cycles of a TLP
transfer.
Transmit Handshake
The handshake signals control the flow of data between the user application and the
integrated Endpoint block.
When the user application has a packet ready for transmission, it asserts
LLKTXCHTC and
LLKTXCHFIFO to select the channel, and asserts LLKTXSRCRDYN to indicate that the data
bus and framing signals are set to transfer data. The user application does not need to wait
for the integrated Endpoint block to assert
LLKTXDSTRDYN. Either ready signal can be
asserted first. See Figure 2-6, page 31.
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