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UG197 (v1.5) July 22, 2009
Extended Capabilities
R
Two linked lists are defined. The method used to disable capabilities depends on which list
includes the capability. The capabilities in the first list are defined in the following order:
PM, MSI, XP (PCIE).
The start of the first linked list is defined by
CAPABILITIESPOINTER, which should be set to
the base pointer of the first enabled capability in the above list. The next pointer for the first
enabled capability is set to the base pointer of the second enabled capability (if there is
one), and so on. The next pointer for the last enabled capability is set to 0, as is done with
PCIECAPABILITYNEXTPTR in the default settings. The default values of the base pointers
for the capabilities in this first list are always used.
The second list includes the following capabilities in order: AER, PB, DSN, VC.
Only the DSN extended capability is supported by the integrated Endpoint block. This
leaves only the option of having the DSN enabled or none enabled as shown in Table A-6.
The base pointer for the first enabled capability in the second list is set to 100h. If the first
enabled capability is DSN, then all the capabilities will use the default base pointers shown
in Table A-5.
Table A-6 lists the possible base pointer settings based on the first enabled capability.
The next pointer for each enabled capability is set to the base pointer of the next enabled
capability. The next pointer for the last enabled capability is set to 0.
The next pointer for an unused capability (in either list) should be left at its default value,
since the next pointer is not used.
PMCAPABILITYNEXTPTR
MSIBASEPTR
MSICAPABILITYNEXTPTR
XPBASEPTR
Should not be changed for PCIe
compliant systems.
PCIECAPABILITYNEXTPTR 0 Cannot be changed.
AERCAPABILITYNEXTPTR
PBBASEPTR
Cannot be changed.
PBCAPABILITYNEXTPTR
DSNBASEPTR
Cannot be changed.
DSNCAPABILITYNEXTPTR
VCBASEPTR
VCCAPABILITYNEXTPTR 0 Cannot be changed.
Tab le A -6 : Possible Combinations of Base Pointer Settings
DSN Enabled None Enabled
(1)
DSNBASEPTR = 100h
(2)
AERBASEPTR = 110h
AERBASEPTR = 10Ch PBBASEPTR = 138h
PBBASEPTR = 144h DSNBASEPTR = 148h
VCBASEPTR = 154h VCBASEPTR = 154h
Notes:
1. Because there are no extended capability base pointers mapped to address 100h, all extended
capabilities are disabled.
2. Set DSNCAPABILITYNEXTPTR to 0 to disable the remaining base pointers in the linked list.
Tab le A -5 : Default Pointer Attribute Settings (Continued)
Attribute Value Notes
- Virtex-5 FPGA 1
- Integrated Endpoint Block 1
- Revision History 3
- VC1*, LOWPRIORITYVCCOUNT 4
- Table of Contents 5
- About This Guide 9
- Additional Documentation 10
- Additional Support Resources 11
- Typographical Conventions 11
- Preface: About This Guide 12
- Block Overview 13
- Memory Requirements 15
- Use Models 15
- Chapter 2 17
- Transaction Layer 18
- Data Link Layer 19
- Physical Layer 19
- Physical Layer Lane Module 20
- Clock Frequency 21
- Integrated 22
- Endpoint Block 22
- Transmit 28
- Channels 29
- Channel Ready 29
- Channel Select 29
- Transmit Framing 29
- Framing Errors 30
- DWORD Enables 30
- Transmit Handshake 30
- UG197_c2_04_030607 31
- Receive Framing 32
- Receive Handshake 32
- UG197_c2_06_111906 34
- Management Interface 37
- UG197_c2_08_082406 38
- Block RAM Interface 40
- RX and TX Buffer Capacity 41
- Retry Buffer Size 41
- Transceiver Interface 42
- Power Management Interface 45
- Registers 53
- Table 2-19: MSI Registers 55
- Reserved Registers 56
- Chapter 3 63
- Chapter 4 65
- Configuration Requests 66
- Transaction Ordering 67
- Interrupt Handling 68
- INTERRUPTDISABLE output: 69
- Error Detection 70
- Error Reporting 74
- Message Tags 76
- Phantom Function Support 76
- Lane Width 77
- Lane Reversal 77
- Workaround 78
- Appendix A 91
- TOTALCREDITS attributes are 92
- Initial Flow Control Credits 93
- Extended Capabilities 94
- The offset to the next PCI 105
- Contains the offset of 105
- UG197 (v1.5) July 22, 2009 108
- Glossary 109
- Function 112
- Hot plug 112
- Hot swap 112
- Isochronous data transfer 112
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