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94 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block
UG197 (v1.5) July 22, 2009
Appendix A: Integrated Endpoint Block Attributes
R
• Infinite Completions are indicated by setting the flow control credit attribute to 0, and
setting the
INFINITECOMPLETIONS attribute to TRUE.
• Each posted data credit is 16 bytes.
• The maximum number of packets that can be buffered by each FIFO is eight. Thus, the
maximum number of posted data or completion data credits that should be
advertised is 8 ×
XPMAXPAYLOAD/16.
Extended Capabilities
The integrated Endpoint block supports several Extended Capabilities:
• Power Management (PM)
• Message Signaled Interrupt (MSI)
• PCI Express (XP or PCIe)
• Device Serial Number (DSN)
Attributes are defined for pointers to these capability structures. In addition, there are
attributes for pointers to capabilities that are included in the PCI Express specification but
not supported by the Virtex-5 FPGA Integrated Endpoint Block:
• Advanced Error Reporting (AER)
• Power Budgeting (PB)
• Virtual Channel (VC)
Note:
The Virtex-5 FPGA Integrated Endpoint Block supports the VC Capability Structure; however,
the recommended and supported design flow for utilizing the integrated Endpoint block (via the
CORE Generator tool to create the Endpoint Block Plus wrapper) disables the VC Extended
Capability structure. The default attribute settings listed in this appendix reflect the capabilities of the
Endpoint Block Plus wrapper.
The PCI Express and Power Management capabilities should be enabled in PCI Express
compliant implementations. The MSI and DSN capabilities can be enabled or disabled,
depending on the application.
A base pointer and a next pointer must be set for each extended capability, depending on
which capabilities are chosen. Each pointer has a default value, which is used if all
available capabilities are enabled. If one or more capabilities are disabled, then the
appropriate pointers must be changed.
Tab le A -5 : Default Pointer Attribute Settings
Attribute Value Notes
PMBASEPTR 40h Cannot be changed.
MSIBASEPTR 48h Cannot be changed.
XPBASEPTR 60h Cannot be changed.
AERBASEPTR 110h See Table A-6 for other legal values.
PBBASEPTR 138h See Table A-6 for other legal values.
DSNBASEPTR 148h See Table A-6 for other legal values.
VCBASEPTR 154h See Table A-6 for other legal values.
CAPABILITIESPOINTER
PMBASEPTR
Should not be changed for PCIe
compliant systems.
- Virtex-5 FPGA 1
- Integrated Endpoint Block 1
- Revision History 3
- VC1*, LOWPRIORITYVCCOUNT 4
- Table of Contents 5
- About This Guide 9
- Additional Documentation 10
- Additional Support Resources 11
- Typographical Conventions 11
- Preface: About This Guide 12
- Block Overview 13
- Memory Requirements 15
- Use Models 15
- Chapter 2 17
- Transaction Layer 18
- Data Link Layer 19
- Physical Layer 19
- Physical Layer Lane Module 20
- Clock Frequency 21
- Integrated 22
- Endpoint Block 22
- Transmit 28
- Channels 29
- Channel Ready 29
- Channel Select 29
- Transmit Framing 29
- Framing Errors 30
- DWORD Enables 30
- Transmit Handshake 30
- UG197_c2_04_030607 31
- Receive Framing 32
- Receive Handshake 32
- UG197_c2_06_111906 34
- Management Interface 37
- UG197_c2_08_082406 38
- Block RAM Interface 40
- RX and TX Buffer Capacity 41
- Retry Buffer Size 41
- Transceiver Interface 42
- Power Management Interface 45
- Registers 53
- Table 2-19: MSI Registers 55
- Reserved Registers 56
- Chapter 3 63
- Chapter 4 65
- Configuration Requests 66
- Transaction Ordering 67
- Interrupt Handling 68
- INTERRUPTDISABLE output: 69
- Error Detection 70
- Error Reporting 74
- Message Tags 76
- Phantom Function Support 76
- Lane Width 77
- Lane Reversal 77
- Workaround 78
- Appendix A 91
- TOTALCREDITS attributes are 92
- Initial Flow Control Credits 93
- Extended Capabilities 94
- The offset to the next PCI 105
- Contains the offset of 105
- UG197 (v1.5) July 22, 2009 108
- Glossary 109
- Function 112
- Hot plug 112
- Hot swap 112
- Isochronous data transfer 112
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