AMX DESIGN XPRESS V 1.5 - PROGRAMMER GUIDE User's Guide Page 61

  • Download
  • Add to my manuals
  • Print
  • Page
    / 120
  • Table of contents
  • BOOKMARKS
  • Rated. / 5. Based on customer reviews
Page view 60
Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 61
UG197 (v1.5) July 22, 2009
Registers
418
12:0
VC0TXFIFOLIMITC RW
13 Reserved
26:14
VC0TXFIFOLIMITNP RW
27 Reserved
419
12:0
VC0TXFIFOLIMITP RW
13 Reserved
26:14
VC0TXFIFOBASEC RW
27 Reserved
41A
12:0
VC0TXFIFOBASENP
RW
13 Reserved
26:14
VC0TXFIFOBASEP RW
27 Reserved
41B
7:0
XPBASEPTR
RW
19:8
VCBASEPTR
RW
31:20
PMBASEPTR
RW
41C
11:0
PBBASEPTR
RW
23:12
MSIBASEPTR
RW
41D
11:0
DSNBASEPTR
RW
23:12
AERBASEPTR
RW
41E .. 7FF Reserved
Table 2-23: Management Control and Status Registers (Continued)
Management
Address (Hex)
MGMTADDR[10:0]
Bit Position Attribute Name
Read Only or
Read Write
Page view 60
1 ... 60 61 62 ... 120

Comments to this Manuals

No comments