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UG197 (v1.5) July 22, 2009

Virtex-5 FPGA Integrated Endpoint Block Interface Descriptions

When there is no more data to receive, LLKRXDSTREQN must be deasserted in the cycle

after

LLKRXSRCLASTREQN is first asserted. See Figure 2-7. Failure to do this causes the

block to enter an undefined state; as a result, subsequent packets can be corrupted.

Figure 2-7: Transaction Layer Interface Receive Timing Diagram Showing a 4 DW Header and 6 DW Data

Payload

CRMUSERCLK

LLKRXDSTREQN

LLKRXSRCLASTREQN

LLKRXSRCRDYN

LLKRXVALIDN

LLKRXDATA

LLKRXSOFN

LLKRXEOFN

LLKRXCHFIFO

3+TL_RAM_READ_LATENCY

11 11 11 1100

H0 H1 H2 H3 P0 P1 P2 P3 P4 P5

00 00

REQN deasserted after

LASTREQN when asserted in one

or all of the three previous cycles

UG197_c2_05_121306

LLKRXCHTC

1 ... 32 33 34 ... 120

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AMX DESIGN XPRESS V 1.5 - PROGRAMMER GUIDE User's Guide Page 33