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UG197 (v1.5) July 22, 2009

Registers

409

BAR0ADDRWIDTH

BAR1ADDRWIDTH

BAR2ADDRWIDTH

BAR3ADDRWIDTH

BAR4ADDRWIDTH

5 Reserved

40A

BAR0EXIST

BAR1EXIST

BAR2EXIST

BAR3EXIST

BAR4EXIST RW

BAR5EXIST RW

40B

12:0 Reserved

13 Reserved

26:14 Reserved

27 Reserved

40C

12:0 Reserved

13 Reserved

26:14 Reserved

27 Reserved

40D

12:0 Reserved

13 Reserved

26:14 Reserved

27 Reserved

40E

10:0 Reserved

21:11 Reserved

40F

6:0 Reserved

13:7 Reserved

20:14 Reserved

Table 2-23: Management Control and Status Registers (Continued)

Management

Address (Hex)

MGMTADDR[10:0]

Bit Position Attribute Name

Read Only or

Read Write

1 ... 58 59 60 ... 120

Virtex-5 FPGA 1
Integrated Endpoint Block 1
Revision History 3
VC1*, LOWPRIORITYVCCOUNT 4
Table of Contents 5
About This Guide 9
Additional Documentation 10
Additional Support Resources 11
Typographical Conventions 11
Preface: About This Guide 12
Block Overview 13
Memory Requirements 15
Use Models 15
Chapter 2 17
Transaction Layer 18
Data Link Layer 19
Physical Layer 19
Physical Layer Lane Module 20
Clock Frequency 21
Integrated 22
Endpoint Block 22
Transmit 28
Channels 29
Channel Ready 29
Channel Select 29
Transmit Framing 29
Framing Errors 30
DWORD Enables 30
Transmit Handshake 30
UG197_c2_04_030607 31
Receive Framing 32
Receive Handshake 32
UG197_c2_06_111906 34
Management Interface 37
UG197_c2_08_082406 38
Block RAM Interface 40
RX and TX Buffer Capacity 41
Retry Buffer Size 41
Transceiver Interface 42
Power Management Interface 45
Registers 53
Table 2-19: MSI Registers 55
Reserved Registers 56
Chapter 3 63
Chapter 4 65
Configuration Requests 66
Transaction Ordering 67
Interrupt Handling 68
INTERRUPTDISABLE output: 69
Error Detection 70
Error Reporting 74
Message Tags 76
Phantom Function Support 76
Lane Width 77
Lane Reversal 77
Workaround 78
Appendix A 91
TOTALCREDITS attributes are 92
Initial Flow Control Credits 93
Extended Capabilities 94
The offset to the next PCI 105
Contains the offset of 105
UG197 (v1.5) July 22, 2009 108
Glossary 109
Function 112
Hot plug 112
Hot swap 112
Isochronous data transfer 112

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