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46 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block
UG197 (v1.5) July 22, 2009
Chapter 2: Integrated Endpoint Block Functionality
R
Configuration and Status Interface
This interface includes control and status, error, backend interface configuration, and
interrupt ports. More information on error reporting and user application design
considerations can be found in Chapter 4, “Integrated Endpoint Block Operation.” The
ports are listed in Table 2-16.
Table 2-16: Configuration and Status Ports
Port Direction
Clock
Domain
Description
COMPLIANCEAVOID
Input core_clk Modifies the rules for entering
POLLING. COMPLIANCE from
POLLING.ACTIVE (see Section 4.2.6.2.1
of the PCI Express Base Specification).
When 0, the block enters
POLLING.COMPLIANCE if any lane that
detected a receiver during Detect has
not detected an exit from Electrical Idle
since entering
POLLING.ACTIVE.
When 1, the block enters
POLLING.COMPLIANCE if all the lanes
that detected receivers have not
detected exit from Electrical Idle since
entering
POLLING.ACTIVE. This option
is provided to cope with broken lanes
in the receive path.
L0FIRSTCFGWRITEOCCURRED
Output user_clk Asserted following the completion of
the first configuration write after reset.
L0CFGLOOPBACKMASTER
Input core_clk Remote device loopback control, used
to check the physical connectivity of a
link. When asserted, causes the MAC to
send training sequences, which put the
device at the other end of the link into
loopback mode. The remote device
then loops back all packets sent by this
device until
L0CFGLOOPBACKMASTER is
deasserted, causing the link to retrain.
L0CFGLOOPBACKACK
Output core_clk Asserted after the block has entered the
Loopback master state.
L0RXMACLINKERROR[1:0]
Output core_clk Used to report link errors. Bit 1 asserted
indicates a receiver error. Bit 0 asserted
indicates a link training error.
L0MACLINKUP
Output core_clk Driven High when link training has
completed and the link is operational.
- Virtex-5 FPGA 1
- Integrated Endpoint Block 1
- Revision History 3
- VC1*, LOWPRIORITYVCCOUNT 4
- Table of Contents 5
- About This Guide 9
- Additional Documentation 10
- Additional Support Resources 11
- Typographical Conventions 11
- Preface: About This Guide 12
- Block Overview 13
- Memory Requirements 15
- Use Models 15
- Chapter 2 17
- Transaction Layer 18
- Data Link Layer 19
- Physical Layer 19
- Physical Layer Lane Module 20
- Clock Frequency 21
- Integrated 22
- Endpoint Block 22
- Transmit 28
- Channels 29
- Channel Ready 29
- Channel Select 29
- Transmit Framing 29
- Framing Errors 30
- DWORD Enables 30
- Transmit Handshake 30
- UG197_c2_04_030607 31
- Receive Framing 32
- Receive Handshake 32
- UG197_c2_06_111906 34
- Management Interface 37
- UG197_c2_08_082406 38
- Block RAM Interface 40
- RX and TX Buffer Capacity 41
- Retry Buffer Size 41
- Transceiver Interface 42
- Power Management Interface 45
- Registers 53
- Table 2-19: MSI Registers 55
- Reserved Registers 56
- Chapter 3 63
- Chapter 4 65
- Configuration Requests 66
- Transaction Ordering 67
- Interrupt Handling 68
- INTERRUPTDISABLE output: 69
- Error Detection 70
- Error Reporting 74
- Message Tags 76
- Phantom Function Support 76
- Lane Width 77
- Lane Reversal 77
- Workaround 78
- Appendix A 91
- TOTALCREDITS attributes are 92
- Initial Flow Control Credits 93
- Extended Capabilities 94
- The offset to the next PCI 105
- Contains the offset of 105
- UG197 (v1.5) July 22, 2009 108
- Glossary 109
- Function 112
- Hot plug 112
- Hot swap 112
- Isochronous data transfer 112
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