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Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 21

UG197 (v1.5) July 22, 2009

Virtex-5 FPGA Integrated Endpoint Block Interface Descriptions

The following subsections describe the physical interfaces on the integrated Endpoint

block. Connections and control of these interfaces are contained within the Endpoint Block

Plus Wrapper for PCI Express available from the CORE Generator GUI. The Endpoint

Block Plus Wrapper for PCI Express uses the integrated Endpoint block to create a PCI

Express Endpoint in the Virtex-5 FPGA. All users of the integrated Endpoint block should

use the Endpoint Block Plus Wrapper in their designs.

Clock and Reset Interface

Clocks

The integrated Endpoint block has two synchronous clock domains: core_clk and user_clk.

The user_clk domain allows user logic in the fabric to run at a slower speed than the

integrated Endpoint block in x1, x2, or x4 modes. Each clock domain has several clock

ports to improve timing. All clock ports on the same clock domain must be tied to the same

BUFG.

The user_clk domain is controlled by the

CRMUSERCLK, CRMUSERCLKRXO, and

CRMUSERCLKTXO ports (see Table 2-3). The user_clk domain clocks the following:

• The Management interface

• The Transaction Layer interface

• The write port of the TX buffer

• The read port of the RX buffer

• User logic in the fabric connected to the above interfaces

The core_clk domain is controlled by the

CRMCORECLK, CRMCORECLKRXO,

CRMCORECLKTXO, and CRMCORECLKDLO signals (see Table 2-3). The core_clk domain

clocks the following:

• The rest of the integrated Endpoint block

• The read port of the TX buffer

• The write port of the RX buffer

• The Retry buffer

• The Transceiver interface

• Portions of the RocketIO transceiver (

TXUSRCLK2, RXUSRCLK2)

Clock Frequency

The core_clk always runs at 250 MHz. The user_clk must also run at 250 MHz for x8

configurations to maintain full bandwidth. The user_clk can be run at lower frequencies

for x1, x2, or x4, while still maintaining full bandwidth, lowering power, and simplifying

timing closure. Table 2-1 shows the allowed clock frequencies.

Table 2-1: Clock Frequency Versus Lane Width

Configured Lane Width core_clk Frequency (MHz) user_clk Frequency (MHz)

(1)

x1 250 62.5, 125, or 250

x2 250 62.5, 125, or 250

1 ... 20 21 22 ... 120

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