AMX DESIGN XPRESS V 1.5 - PROGRAMMER GUIDE manuals

Owner’s manuals and user’s guides for TVs & monitors AMX DESIGN XPRESS V 1.5 - PROGRAMMER GUIDE.
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Amx DESIGN XPRESS V 1.5 - PROGRAMMER GUIDE User's Guide (120 pages)

Brand: Amx | Category: TVs & monitors | Size: 1.56 MB |

English

Table of contents

Virtex-5 FPGA

1

Integrated Endpoint Block

1

Revision History

3

VC1*, LOWPRIORITYVCCOUNT

4

Table of Contents

5

About This Guide

9

Additional Documentation

10

Additional Support Resources

11

Typographical Conventions

11

Preface: About This Guide

12

Block Overview

13

Memory Requirements

15

Use Models

15

Chapter 2

17

Transaction Layer

18

Data Link Layer

19

Physical Layer

19

Physical Layer Lane Module

20

Clock Frequency

21

Integrated

22

Endpoint Block

22

Transmit

28

Channels

29

Channel Ready

29

Channel Select

29

Transmit Framing

29

Framing Errors

30

DWORD Enables

30

Transmit Handshake

30

UG197_c2_04_030607

31

Receive Framing

32

Receive Handshake

32

UG197_c2_06_111906

34

Management Interface

37

UG197_c2_08_082406

38

Block RAM Interface

40

RX and TX Buffer Capacity

41

Retry Buffer Size

41

Transceiver Interface

42

Power Management Interface

45

Registers

53

Table 2-19: MSI Registers

55

Reserved Registers

56

Chapter 3

63

Chapter 4

65

Configuration Requests

66

Transaction Ordering

67

Interrupt Handling

68

INTERRUPTDISABLE output:

69

Error Detection

70

Error Reporting

74

Message Tags

76

Phantom Function Support

76

Lane Width

77

Lane Reversal

77

Workaround

78

Appendix A

91

TOTALCREDITS attributes are

92

Initial Flow Control Credits

93

Extended Capabilities

94

The offset to the next PCI

105

Contains the offset of

105

UG197 (v1.5) July 22, 2009

108

Glossary

109

Function

112

Hot plug

112

Hot swap

112

Isochronous data transfer

112

Amx DESIGN XPRESS V 1.5 - PROGRAMMER GUIDE User's Guide (316 pages)

Brand: Amx | Category: TVs & monitors | Size: 1.29 MB |

English

Table of contents

KwikNet

1

All rights reserved

4

DISCLAIMER

4

TRADEMARKS

4

Copyright Notice

5

KwikNet User's Guide

14

1. KwikNet Overview

15

1.1 Introduction

15

1.2 General Operation

21

Application

22

1.3 KwikNet Nomenclature

27

1.8 KwikNet Console Driver

37

1.9 Debugging Aids

39

2.1 Introduction

49

View Toolbar

52

Edit menu

52

Target Parameters

58

OS Parameters

60

General Stack Parameters

64

IPv4 Stack Parameters

67

TCP Stack Parameters

70

Ethernet Parameters

73

DNS Client Parameters

79

Optional Components

81

Debug and Logging Parameters

83

SLIP IP Address Definition

99

KwikNet System Configuration

103

KwikNet Modem Driver

103

Modem Options

103

Networks

108

PPP IP Address Definition

110

Edit: Network radio

112

PPP Options... button

112

2.7 Modem Options

113

3.1 Building an Application

117

KwikNet System Construction

119

KwikNet Library Construction

119

3.5 Linking the Application

125

3.7 Using KwikNet with AMX

130

3.7.3 Toolset Considerations

134

4.2 DHCP, BOOTP and Auto IP

141

KwikNet Low Level Services

142

4.3 The DNS Client

145

TM_EWOULDBLOCK

146

4.4 ICMP Protocol

147

4.6 KwikNet Library Services

157

...continued

191

5. KwikNet TCP/IP Sockets

195

5.1 Introduction to

195

Sockets

195

5.2 Socket Types

198

5.3 Socket Options

201

KwikNet TCP/IP Sockets

204

5.4 KwikNet Socket Services

205

6. KwikNet PPP Option

239

6.1 Introduction to PPP

239

KwikNet PPP Option

241

PPP Network Definition

242

PPP Options

243

7.1 Introduction

253

7.3 Using the VFS Generator

265

7.4 Multiple VFS Volumes

271

7.5 VFS Service Procedures

272

A.1 Reference Materials

281

A.2 KwikNet Glossary

283

B. KwikNet Error Codes

289

KwikNet Error Codes

294

C.1 Introduction

295

C.1.1 Treck File Systems

295

D.1 Introduction

305

Amx DESIGN XPRESS V 1.5 - PROGRAMMER GUIDE User Manual (52 pages)

Brand: Amx | Category: TVs & monitors | Size: 3.36 MB |

English

Table of contents

Getting Started Guide

1

Chapter 1

3

Chapter 2

3

Chapter 3

3

Chapter 4

3

Contents

4

How to Use This Guide

6

How to Obtain Support

7

Before You Begin

8

Introduction

10

Installing the Software

11

Chapter 1 Before You Begin

12

Quantification Assays

14

Overview

15

To load a sequence file:

16

Finding Primers

17

Saving the

19

Document

19

Ordering Primers

19

If primers were not found:

22

To design the Reverse Primer:

24

Green Dye

26

Green Dye Assays

27

Allelic Discrimination Assays

34

Assigning a SNP

37

To design the Forward Primer:

44

Ordering Primers and Probes

46

Part Number 4362460 Rev. B

52

Amx DESIGN XPRESS V 1.5 - PROGRAMMER GUIDE Specifications (26 pages)

Brand: Amx | Category: TVs & monitors | Size: 0.29 MB |

English

Table of contents

20.00 Electrical Services

1

20.03 Lighting Control

4

20.07 Power

9

20.10 General Wiring

16

20.13 Lightning Protection

20

20.14 Clocks

20

20.16 High Voltage System

22

20.17 Testing

22

20.19 Deliverables

24

METER INSTALLATION RECORD

26

Amx DESIGN XPRESS V 1.5 - PROGRAMMER GUIDE User's Guide (288 pages)

Brand: Amx | Category: TVs & monitors | Size: 5.68 MB |

English

Table of contents

User Guide

1

Contents

3

Chapter 7. IP Core Interfaces

4

Chapter 9. Reset and Clocks

5

Chapter 18. Debugging

8

1. Datasheet

9

1–2 Chapter 1: Datasheet

10

Features

10

Notes to Table 1–2:

11

Release Information

12

Device Family Support

12

Configurations

12

Debug Features

13

IP Core Verification

14

Recommended Speed Grades

15

1–8 Chapter 1: Datasheet

16

Hard IP for PCI Express

17

Qsys Design Flow

25

Generating the Testbench

26

Simulating the Example Design

27

Modifying the Example Design

34

Running Qsys

36

Table 3–5

38

On Chip r

40

Direct BFM’s shared memory

47

{*reconfig_xcvr_clk*}

50

Compiling the Design

51

Programming a Device

51

System Settings

54

Port Functions

55

Error Reporting

57

31 19 18 17 16 15 14

58

Power Management

59

Legacy Interrupt

63

Base Address Registers

66

PCI Express/PCI Capabilities

67

Header

68

6. IP Core Architecture

75

Avalon-ST Interface

77

RX Datapath

77

TX Datapath

77

Altera FPGA

77

Clocks and Reset

78

Interrupts

79

Transaction Layer

79

Protocol Layers

80

Configuration Space

81

Data Link Layer

81

Figure 6–4. Data Link Layer

82

Physical Layer

83

Figure 6–5. Physical Layer

84

Multi-Function Support

86

PCI Express Avalon-MM Bridge

86

Avalon-MM Bridge TLPs

88

Figure 6–9. Poor Address Map

93

RX Block

97

Avalon-MM RX Master Block

97

TX Block

98

Interrupt Handler Block

98

7. IP Core Interfaces

99

Note to Table 7–1:

100

RX Port

102

Avalon-ST RX Interface

104

Note to Figure 7–8:

109

Avalon-ST TX Interface

114

Note to Table 7–4:

117

ECRC Forwarding

122

Clock Signals

122

Reset Signals

123

and the LTSSM L0 state

125

ECC Error Signals

126

Interrupts for Endpoints

126

Interrupts for Root Ports

127

Completion Side Band Signals

127

Specification, Rev. 2.1

129

D E F 0 1 2 3

132

Notes to Table 7–12:

133

LMI Signals

137

LMI Read Operation

138

LMI Write Operation

138

Power Management Signals

139

(Full-Featured Qsys)

141

Completer-Only Single DWord

142

RX Avalon-MM Master Signals

144

Transceiver Reconfiguration

146

Serial Interface Signals

146

PIPE Interface Signals

150

Test Signals

153

Notes to Table 7–26:

154

8. Register Descriptions

155

Note to Table 8–2:

156

Note to Table 8–3:

157

Note to Table 8–4:

157

Note to Table 8–5:

157

Note to Table 8–6:

158

Note to Table 8–7:

158

Note to Table 8–8:

159

s and wait

162

PCI Express Mailbox Registers

167

Note to Table 8–30:

168

Root Port TLP Data Registers

170

Sending a TLP

173

Receiving a Completion TLP

173

Endpoints

174

Avalon-MM Mailbox Registers

175

Spec 2.1

176

9. Reset and Clocks

181

Example Design

182

127 cycles

184

300 PPM

185

Transceiver Clock Signals

186

Supported Message Types

189

Notes to Table 10–1:

191

Receive Buffer Reordering

192

Notes to Table 10–2:

193

MSI Interrupts

195

11–2 Chapter 11: Interrupts

196

Note to Figure 11–4:

197

Legacy Interrupts

198

Application Layer

199

11–6 Chapter 11: Interrupts

200

MSI/MSI-X Support

201

Qsys System

202

12. Optional Features

203

ECRC on the RX Path

204

ECRC on the TX Path

205

13. Flow Control

207

13–2 Chapter 13: Flow Control

208

Throughput of Posted Writes

208

Chapter 13: Flow Control 13–3

209

13–4 Chapter 13: Flow Control

210

14. Error Handling

211

Physical Layer Errors

212

Data Link Layer Errors

212

Transaction Layer Errors

213

s limit

214

Note to Table 14–4:

215

Figure 15–2

218

Core User Guide

219

16. SDC Timing Constraints

221

Endpoint Testbench

224

Root Port Testbench

225

Chaining DMA Design Examples

226

Root Complex

227

Chaining DMA

227

Hard IP for

227

PCI Express

227

Note to Table 17–2:

232

Note to Table 17–4:

233

Test Driver Module

236

DMA Write Cycles

237

DMA Read Cycles

239

Root Port Design Example

240

Root Port

241

Variation

241

(variation_name.v)

241

Root Port BFM

242

BFM Memory Map

244

Figure 17–6

248

BFM Read and Write Procedures

250

BFM Procedures and Functions

251

BFM Configuration Procedures

256

Shared Memory Constants

257

18. Debugging

271

18–2 Chapter 18: Debugging

272

Link Training

272

Chapter 18: Debugging 18–3

273

18–4 Chapter 18: Debugging

274

Chapter 18: Debugging 18–5

275

Setting Up Simulation

276

Chapter 18: Debugging 18–7

277

Use Third-Party PCIe Analyzer

278

BIOS Enumeration Issues

278

Notes to Table A–7:

280

Chapter : A–3

281

Notes to Table A–16:

282

Additional Information

283

Info–2 Revision History

284

How to Contact Altera

285

Typographic Conventions

286

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