AMX DESIGN XPRESS V 1.5 - PROGRAMMER GUIDE User's Guide download pdf (Page 3)

UG197 (v1.5) July 22, 2009 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block

Revision History

The following table shows the revision history for this document.

Date Version Revision

09/06/06 1.0 Initial Xilinx release on CD.

03/20/07 1.1 Moved “TX and RX Buffer Layout” and “Buffer Latency” from Chapter 2 to Appendix

A. Renamed Chapter 3 to “Designing with the Endpoint Block Plus Wrapper”and

replaced content. Split Error Reporting table into Table 4-3 (PCIe Block action) and

Table 4-4 (User action). Added VHDL code examples to “Simulating in VHDL” in

Chapter 5.

12/13/07 1.2 Revised L0PWRTURNOFFREQ description in Table 2-15, page 45 and added a footnote

tied to power state D3.

Clarified request types when crossing a 4 KB boundary in

Table 4-2, page 70.

Replaced Chapter 3, “Designing with the Endpoint Block Plus Wrapper.”

Addition of “Known Restrictions,” page 78.

06/02/08 1.3 Updated “TX Transmission Issues Due to Lack of Data Credits,” page 78 including

workaround.

Added “Lane Reversal,” page 77.

Fixed

LLKRXDSTREQN in “Invalid Cycles in LLKRXPREFERREDTYPE Signal,” page 81.

Updated “Credit Leak When Transmitting Completion TLPs,” page 86.

Added “Receipt of Back-to-Back ACK DLLPs,” page 87.

1 2 3 4 ... 120

No comments

AMX DESIGN XPRESS V 1.5 - PROGRAMMER GUIDE User's Guide Page 3