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36 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block
UG197 (v1.5) July 22, 2009
Chapter 2: Integrated Endpoint Block Functionality
R
LLKRXSRCRDYN
Output user_clk Asserted (active Low) for one cycle if the receive
source has data available on
LLKRXDATA in response
to an earlier LLKRXDSTREQN. Data must be
captured by the user design during the cycle
LLKRXSRCRDYN is asserted. LLKRXSRCRDYN
reflects the value of LLKRXVALID[1:0].
LLKRXSRCRDYN = 1 when LLKRXVALIDN = 11.
LLKRXSRCRDYN = 0 when either bit of
LLKRXVALIDN = 0.
LLKRXDSTREQN
Input user_clk Receive data destination request (active Low).
See
LLKRXSRCLASTREQN.
LLKRXSRCLASTREQN
Output user_clk Asserted three cycles after the block has received the
penultimate request for the current RX packet. If
LLKRXDSTREQN was asserted in one of the three
cycles, then the block has received the final request
for the current RX packet. No further requests should
be issued (with assertion of
LLKRXDSTREQN) unless
there are further packets available on the selected
channel as indicated by the corresponding
LLKRXCH*AVAILABLEN signal, where * is POSTED,
NONPOSTED, or COMPLETION (active Low).
LLKRXDSTCONTREQN
Input user_clk When this signal is asserted, every assertion of
LLKRXDSTREQN requests data from the selected
channel, which allows continuous requests while
receiving back-to-back packets. Should only be
asserted in cases where there is a further packet(s) of
the same type to be received after the current one.
LLKRXSOFN
Output user_clk Transaction Layer interface RX Start of Frame (active
Low).
LLKRXEOFN
Output user_clk Transaction Layer interface RX End of Frame (active
Low).
LLKRXSOPN
Output user_clk Not supported. Must be tied High.
LLKRXEOPN
Output user_clk Not supported. Must be tied High.
LLKRXVALIDN[1:0]
Output user_clk Word enable for Transaction Layer interface receive
bus (active Low).
LLKRXCHTC[2:0]
Input user_clk Traffic class portion of Channel Select.
LLKRXCHFIFO[1:0]
Input user_clk FIFO portion of Channel Select.
00:Posted
01: Non-posted
10:Completion
11: Reserved
LLKRXCHPOSTEDAVAILABLEN[7:0]
Output user_clk Traffic classes with complete posted packets
available (active Low).
Table 2-6: Transaction Layer Interface Ports (Continued)
Port Direction
Clock
Domain
Description
- Virtex-5 FPGA 1
- Integrated Endpoint Block 1
- Revision History 3
- VC1*, LOWPRIORITYVCCOUNT 4
- Table of Contents 5
- About This Guide 9
- Additional Documentation 10
- Additional Support Resources 11
- Typographical Conventions 11
- Preface: About This Guide 12
- Block Overview 13
- Memory Requirements 15
- Use Models 15
- Chapter 2 17
- Transaction Layer 18
- Data Link Layer 19
- Physical Layer 19
- Physical Layer Lane Module 20
- Clock Frequency 21
- Integrated 22
- Endpoint Block 22
- Transmit 28
- Channels 29
- Channel Ready 29
- Channel Select 29
- Transmit Framing 29
- Framing Errors 30
- DWORD Enables 30
- Transmit Handshake 30
- UG197_c2_04_030607 31
- Receive Framing 32
- Receive Handshake 32
- UG197_c2_06_111906 34
- Management Interface 37
- UG197_c2_08_082406 38
- Block RAM Interface 40
- RX and TX Buffer Capacity 41
- Retry Buffer Size 41
- Transceiver Interface 42
- Power Management Interface 45
- Registers 53
- Table 2-19: MSI Registers 55
- Reserved Registers 56
- Chapter 3 63
- Chapter 4 65
- Configuration Requests 66
- Transaction Ordering 67
- Interrupt Handling 68
- INTERRUPTDISABLE output: 69
- Error Detection 70
- Error Reporting 74
- Message Tags 76
- Phantom Function Support 76
- Lane Width 77
- Lane Reversal 77
- Workaround 78
- Appendix A 91
- TOTALCREDITS attributes are 92
- Initial Flow Control Credits 93
- Extended Capabilities 94
- The offset to the next PCI 105
- Contains the offset of 105
- UG197 (v1.5) July 22, 2009 108
- Glossary 109
- Function 112
- Hot plug 112
- Hot swap 112
- Isochronous data transfer 112
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