AMX DESIGN XPRESS V 1.5 - PROGRAMMER GUIDE User's Guide Page 119
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Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 119
UG197 (v1.5) July 22, 2009
R
Next Pointer register 55
P
PARITYERRORRESPONSE port 52
PBBASEPTR attribute 94, 95, 105
PBCAPABILITYDW0BASEPOWER at-
tribute
105
PBCAPABILITYDW0DATASCALE at-
tribute
106
PBCAPABILITYDW0PMSTATE attribute
106
PBCAPABILITYDW0PMSUBSTATE at-
tribute
106
PBCAPABILITYDW0POWERRAIL at-
tribute
106
PBCAPABILITYDW0TYPE attribute 106
PBCAPABILITYDW1BASEPOWER at-
tribute
106
PBCAPABILITYDW1DATASCALE at-
tribute
106
PBCAPABILITYDW1PMSTATE attribute
106
PBCAPABILITYDW1PMSUBSTATE at-
tribute
106
PBCAPABILITYDW1POWERRAIL at-
tribute
106
PBCAPABILITYDW1TYPE attribute 106
PBCAPABILITYDW2BASEPOWER at-
tribute
106
PBCAPABILITYDW2DATASCALE at-
tribute
106
PBCAPABILITYDW2PMSTATE attribute
106
PBCAPABILITYDW2PMSUBSTATE at-
tribute
106
PBCAPABILITYDW2POWERRAIL at-
tribute
106
PBCAPABILITYDW2TYPE attribute 106
PBCAPABILITYDW3BASEPOWER at-
tribute
106
PBCAPABILITYDW3DATASCALE at-
tribute
106
PBCAPABILITYDW3PMSTATE attribute
106
PBCAPABILITYDW3PMSUBSTATE at-
tribute
106
PBCAPABILITYDW3POWERRAIL at-
tribute
106
PBCAPABILITYDW3TYPE attribute 106
PBCAPABILITYNEXTPTR attribute 95,
105
PBCAPABILITYSYSTEMALLOCATED at-
tribute
106
PCI COMMAND register 69
pci_xp_link_status register 55
PCIECAPABILITYNEXTPTR attribute 95,
104
Pending Bits register 55
PIPEDESKEWLANESLN port 44
PIPEPHYSTATUSLN port 43
PIPEPOWERDOWNLN bus 44
PIPERESETLN port 44
PIPERXCHANISALIGNEDLN port 43
PIPERXDATAKLN port 43
PIPERXDATALN bus 43
PIPERXELECIDLE port 43
PIPERXPOLARITYLN port 44
PIPERXSTATUSLN bus 43
PIPERXVALIDLN port 43
PIPETXCOMPLIANCELN port 44
PIPETXDATAKLN port 44
PIPETXDATALN bus 43
PIPETXDETECTRXLOOPBACKLN port
44
PIPETXELECIDLELN port 44
PMBASEPTR attribute 94, 107
PMCAPABILITYAUXCURRENT attribute
103
PMCAPABILITYD1SUPPORT attribute
103
PMCAPABILITYD2SUPPORT attribute
103
PMCAPABILITYDSI attribute 103
PMCAPABILITYNEXTPTR attribute 95,
102
PMCAPABILITYPMESUPPORT attribute
103
PMDATA0 attribute 103
PMDATA1 attribute 103
PMDATA2 attribute 103
PMDATA3 attribute 103
PMDATA4 attribute 103
PMDATA5 attribute 103
PMDATA6 attribute 103
PMDATA7 attribute 103
PMDATASCALE0 attribute 103
PMDATASCALE1 attribute 103
PMDATASCALE2 attribute 103
PMDATASCALE3 attribute 103
PMDATASCALE4 attribute 103
PMDATASCALE5 attribute 103
PMDATASCALE6 attribute 103
PMDATASCALE7 attribute 103
PMDATASCALE8 attribute 103
PORTVCCAPABILITYEXTENDEDVC-
COUNT
attribute 105
PORTVCCAPABILITYVCARBCAP at-
tribute
105
PORTVCCAPABILITYVCARBTABLEOFF-
SET
attribute 105
Power Management Capabilities register
54
Power Management Control / Status
(PMCSR)
register 54
R
RESETMODE attribute 23, 24, 26, 38, 106
Retry buffer 15, 19, 21, 25, 40, 41, 42, 91,
92, 98
RETRYRAMREADLATENCY attribute 57,
98
RETRYRAMSIZE attribute 57, 98
RETRYRAMWRITELATENCY attribute
57, 98
Revision ID register 53
REVISIONID attribute 102
RocketIO transceiver
PHYSTATUS port 43
RXCDRRESET port 44
RXCHANISALIGNED port 43
RXCHARISK port 43
RXDATA bus 43
RXELECIDLE port 43
RXPOLARITY port 44
RXPOWERDOWN port 44
RXSTATUS bus 43
RXVALID port 43
TXCHARDISPMODE port 44
TXCHARDISPVAL port 44
TXCHARISK port 44
TXDATA bus 43
TXDETECTRX port 44
TXELECIDLE port 44
TXPOWERDOWN port 44
rom_base_addr_mask register 53
RX buffer 15, 21, 25, 40, 41, 42, 91, 92, 98
S
Serial Number Register (Lower DW) regis-
ter
56
Serial Number Register (Upper DW) regis-
ter
56
SERRENABLE port 52
status register 53
Subsystem ID register 53
Subsystem Vendor ID register 53
SUBSYSTEMID attribute 102
SUBSYSTEMVENDORID attribute 102
- Virtex-5 FPGA 1
- Integrated Endpoint Block 1
- Revision History 3
- VC1*, LOWPRIORITYVCCOUNT 4
- Table of Contents 5
- About This Guide 9
- Additional Documentation 10
- Additional Support Resources 11
- Typographical Conventions 11
- Preface: About This Guide 12
- Block Overview 13
- Memory Requirements 15
- Use Models 15
- Chapter 2 17
- Transaction Layer 18
- Data Link Layer 19
- Physical Layer 19
- Physical Layer Lane Module 20
- Clock Frequency 21
- Integrated 22
- Endpoint Block 22
- Transmit 28
- Channels 29
- Channel Ready 29
- Channel Select 29
- Transmit Framing 29
- Framing Errors 30
- DWORD Enables 30
- Transmit Handshake 30
- UG197_c2_04_030607 31
- Receive Framing 32
- Receive Handshake 32
- UG197_c2_06_111906 34
- Management Interface 37
- UG197_c2_08_082406 38
- Block RAM Interface 40
- RX and TX Buffer Capacity 41
- Retry Buffer Size 41
- Transceiver Interface 42
- Power Management Interface 45
- Registers 53
- Table 2-19: MSI Registers 55
- Reserved Registers 56
- Chapter 3 63
- Chapter 4 65
- Configuration Requests 66
- Transaction Ordering 67
- Interrupt Handling 68
- INTERRUPTDISABLE output: 69
- Error Detection 70
- Error Reporting 74
- Message Tags 76
- Phantom Function Support 76
- Lane Width 77
- Lane Reversal 77
- Workaround 78
- Appendix A 91
- TOTALCREDITS attributes are 92
- Initial Flow Control Credits 93
- Extended Capabilities 94
- The offset to the next PCI 105
- Contains the offset of 105
- UG197 (v1.5) July 22, 2009 108
- Glossary 109
- Function 112
- Hot plug 112
- Hot swap 112
- Isochronous data transfer 112
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