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44 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block
UG197 (v1.5) July 22, 2009
Chapter 2: Integrated Endpoint Block Functionality
R
PIPETXDATAKLn
Output core_clk Control bits for the transmit data.
0: Data byte
1: Control byte
Connect to the
TXCHARISK[0] port on the RocketIO
transceiver.
PIPETXELECIDLELn
Output core_clk Electrical idle requested on transmit channel of selected
lane. When 1, selects electrical idle on Transmit channel
of selected lane. When 0, indicates that there is valid data
on
PIPETXDATALn. Connect to the TXELECIDLE port on
the RocketIO transceiver.
PIPETXDETECTRXLOOPBACKLn
Output core_clk Causes the RocketIO transceiver on the selected lane to
begin receiver detection operation
(
PIPEPOWERDOWNLn=P1) or to begin loopback
(
PIPEPOWERDOWNLn=P0). Connect to the
TXDETECTRX port on the RocketIO transceiver.
PIPETXCOMPLIANCELn
Output core_clk When 1, sets the running disparity for the selected lane to
negative. (Used when transmitting the compliance
pattern). Connect to the
TXCHARDISPMODE[0] port on
the RocketIO transceiver. RocketIO port
TXCHARDISPVAL[0] should be tied to 0.
PIPERXPOLARITYLn
Output core_clk When 1, tells the RocketIO transceiver on selected lane
to do a polarity inversion (on the received data). Connect
to the
RXPOLARITY port on the RocketIO transceiver.
PIPEPOWERDOWNLn[1:0]
Output core_clk Power up/down signal for the transmitter for lane.
00:P0 - Normal Operation
01:P0s - Low recovery time power saving state
10:P1 - Longer recovery time power state
11:P2 - Lowest Power State
Connect to the
TXPOWERDOWN[1:0] and
RXPOWERDOWN[1:0] ports on the RocketIO transceiver.
PIPEDESKEWLANESLn
Output core_clk Enable Channel bonding. Not connected to the RocketIO
transceiver.
PIPERESETLn
Output core_clk Active-High RocketIO transceiver reset. Connect to the
RXCDRRESET port on the RocketIO transceiver.
Table 2-14: RocketIO Transceiver Interface Ports (Continued)
Port Direction
Clock
Domain
Description
- Virtex-5 FPGA 1
- Integrated Endpoint Block 1
- Revision History 3
- VC1*, LOWPRIORITYVCCOUNT 4
- Table of Contents 5
- About This Guide 9
- Additional Documentation 10
- Additional Support Resources 11
- Typographical Conventions 11
- Preface: About This Guide 12
- Block Overview 13
- Memory Requirements 15
- Use Models 15
- Chapter 2 17
- Transaction Layer 18
- Data Link Layer 19
- Physical Layer 19
- Physical Layer Lane Module 20
- Clock Frequency 21
- Integrated 22
- Endpoint Block 22
- Transmit 28
- Channels 29
- Channel Ready 29
- Channel Select 29
- Transmit Framing 29
- Framing Errors 30
- DWORD Enables 30
- Transmit Handshake 30
- UG197_c2_04_030607 31
- Receive Framing 32
- Receive Handshake 32
- UG197_c2_06_111906 34
- Management Interface 37
- UG197_c2_08_082406 38
- Block RAM Interface 40
- RX and TX Buffer Capacity 41
- Retry Buffer Size 41
- Transceiver Interface 42
- Power Management Interface 45
- Registers 53
- Table 2-19: MSI Registers 55
- Reserved Registers 56
- Chapter 3 63
- Chapter 4 65
- Configuration Requests 66
- Transaction Ordering 67
- Interrupt Handling 68
- INTERRUPTDISABLE output: 69
- Error Detection 70
- Error Reporting 74
- Message Tags 76
- Phantom Function Support 76
- Lane Width 77
- Lane Reversal 77
- Workaround 78
- Appendix A 91
- TOTALCREDITS attributes are 92
- Initial Flow Control Credits 93
- Extended Capabilities 94
- The offset to the next PCI 105
- Contains the offset of 105
- UG197 (v1.5) July 22, 2009 108
- Glossary 109
- Function 112
- Hot plug 112
- Hot swap 112
- Isochronous data transfer 112
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