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UG197 (v1.5) July 22, 2009
Virtex-5 FPGA Integrated Endpoint Block Interface Descriptions
R
The CRMPWRSOFTRESETN output indicates when the integrated Endpoint block
transitions from the
D3
hot
power state to the D0
uninitialized
state. This transition must be
used to trigger the assertion of the
CRMUSERCFGRSTN port on the integrated Endpoint
block. This is done in the CORE Generator wrappers.
Ports
Table 2-3 shows the Clock and Reset interface ports.
Table 2-3: Clock and Reset Ports
Port Direction
Clock
Domain
Description
CRMCORECLK
Input core_clk 250 MHz clock from the FPGA, also drives TX buffer read clock
port, RX buffer write clock ports, both Retry buffer clock ports,
and the transceiver
RX/TXUSRCLK2 ports. Should be tied Low if
the integrated Endpoint block is not used.
CRMCORECLK,
CRMCORECLKRXO, CRMCORECLKTXO, and
CRMCORECLKDLO must be tied to the output of the same BUFG.
CRMCORECLKDLO
Input core_clk 250 MHz clock from the FPGA. Clocks the outputs of both Retry
buffer ports. Should be tied Low if the integrated Endpoint block
is not used.
CRMCORECLK, CRMCORECLKRXO,
CRMCORECLKTXO, and CRMCORECLKDLO must be tied to the
output of the same BUFG.
CRMCORECLKTXO
Input core_clk 250 MHz clock from the FPGA. Clocks the TX buffer read port
outputs. Should be tied Low if the integrated Endpoint block is
not used.
CRMCORECLK, CRMCORECLKRXO,
CRMCORECLKTXO, and CRMCORECLKDLO must be tied to the
output of the same BUFG.
CRMCORECLKRXO
Input core_clk 250 MHz clock from the FPGA. Clocks the RX buffer write port
outputs. Should be tied Low if the integrated Endpoint block is
not used.
CRMCORECLK, CRMCORECLKRXO,
CRMCORECLKTXO, and CRMCORECLKDLO must be tied to the
output of the same BUFG.
CRMUSERCLK
Input user_clk User clock. Should be tied Low if the integrated Endpoint block
is not used. CRMUSERCLK, CRMUSERCLKRXO, and
CRMUSERCLKTXO must be tied to the output of the same BUFG
when they are at a lower frequency than CRMCORECLK. Must be
tied High when frequency is the same as
CRMCORECLK
(250 MHz).
CRMUSERCLKTXO
Input user_clk User clock. Clocks TX buffer write port outputs. Should be tied
Low if the integrated Endpoint block is not used.
CRMUSERCLK,
CRMUSERCLKRXO, and CRMUSERCLKTXO must be tied to the
output of the same BUFG when they are at a lower frequency
than
CRMCORECLK. Must be tied High when frequency is the
same as CRMCORECLK (250 MHz).
CRMUSERCLKRXO
Input user_clk User clock. Clocks RX buffer read ports outputs. Should be tied
Low if the integrated Endpoint block is not used. CRMUSERCLK,
CRMUSERCLKRXO, and CRMUSERCLKTXO must be tied to the
output of the same BUFG when they are at a lower frequency
than
CRMCORECLK. Must be tied High when frequency is the
same as
CRMCORECLK (250 MHz).
- Virtex-5 FPGA 1
- Integrated Endpoint Block 1
- Revision History 3
- VC1*, LOWPRIORITYVCCOUNT 4
- Table of Contents 5
- About This Guide 9
- Additional Documentation 10
- Additional Support Resources 11
- Typographical Conventions 11
- Preface: About This Guide 12
- Block Overview 13
- Memory Requirements 15
- Use Models 15
- Chapter 2 17
- Transaction Layer 18
- Data Link Layer 19
- Physical Layer 19
- Physical Layer Lane Module 20
- Clock Frequency 21
- Integrated 22
- Endpoint Block 22
- Transmit 28
- Channels 29
- Channel Ready 29
- Channel Select 29
- Transmit Framing 29
- Framing Errors 30
- DWORD Enables 30
- Transmit Handshake 30
- UG197_c2_04_030607 31
- Receive Framing 32
- Receive Handshake 32
- UG197_c2_06_111906 34
- Management Interface 37
- UG197_c2_08_082406 38
- Block RAM Interface 40
- RX and TX Buffer Capacity 41
- Retry Buffer Size 41
- Transceiver Interface 42
- Power Management Interface 45
- Registers 53
- Table 2-19: MSI Registers 55
- Reserved Registers 56
- Chapter 3 63
- Chapter 4 65
- Configuration Requests 66
- Transaction Ordering 67
- Interrupt Handling 68
- INTERRUPTDISABLE output: 69
- Error Detection 70
- Error Reporting 74
- Message Tags 76
- Phantom Function Support 76
- Lane Width 77
- Lane Reversal 77
- Workaround 78
- Appendix A 91
- TOTALCREDITS attributes are 92
- Initial Flow Control Credits 93
- Extended Capabilities 94
- The offset to the next PCI 105
- Contains the offset of 105
- UG197 (v1.5) July 22, 2009 108
- Glossary 109
- Function 112
- Hot plug 112
- Hot swap 112
- Isochronous data transfer 112
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