AMX DESIGN XPRESS V 1.5 - PROGRAMMER GUIDE User's Guide download pdf (Page 80)

80 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block

UG197 (v1.5) July 22, 2009

Chapter 4: Integrated Endpoint Block Operation

However, if the posted packets are large and completions are very short, the completion

buffer is at risk of overflow when draining the posted packet. The risk is higher if multiple

posted or non-posted packets must be drained before switching back to draining

completions. Since the risk of completion buffer overflow depends on the traffic pattern,

there are three potential workarounds:

1. When a predictable traffic pattern with uniform packet sizes is used with Completion

Streaming mode, the user should switch from draining completions to draining

posted/non-posted packets whenever there is danger of build up of posted/non-

posted packets (to avoid completion buffer overflow while draining posted/non-

posted packets) or when there is a danger of completion passing a non-posted packet

outside the 64-packet window

2. In all other cases which use Completion Streaming mode, the flow control credits for

posted packets and non-posted packets should be restricted to one header each. In

addition, preference should be given to draining posted and non-posted packets

whenever there is a packet of that type available in the receive buffer. This preference

controls the transmission of posted and non-posted packets from the partner device

and will always guarantee safe operation independent of traffic pattern.

3. This solution is an alternative to solution #2 and can be used with and without

Completion Streaming mode. The user should turn off infinite completion credits by

setting the attribute

INFINITECOMPLETIONS in the integrated Endpoint block to

FALSE. The user should then switch to draining posted/non-posted packets whenever

there is danger of a completion passing a non-posted packet outside the 64-packet

window. However, turning off infinite completion credits will result in a non-

compliant solution.

Users should choose the option that best suits their applications. LogiCORE Endpoint

Block Plus for PCI Express implements all three solutions and provides them as a user

selectable option.

Reset Considerations in LTSSM Polling State

When the integrated Endpoint block‘s LTSSM is in the polling state and Lane 0 breaks

electrical idle (transitions from 1 to 0), the block is not reset.

Workaround

The user must monitor the PIPERXELECIDLE0 and L0LTSSMSTATE signals and generate an

additional reset to the block when this LTSSM condition occurs. The additional reset must

be applied to all registers except the sticky and management registers. Sample pseudocode

is provided:

additional reset = (PIPERXLECIDLE0 == 1 → 0)

& (L0LTSSMSTATE == 4’b0010)

This workaround is implemented in LogiCORE Endpoint Block Plus for PCI Express

designs v1.3 or later and LogiCORE Endpoint Block for PCI Express Designs v1.4 or later.

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