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UG197 (v1.5) July 22, 2009

Virtex-5 FPGA Integrated Endpoint Block Interface Descriptions

Channels

The Transaction Layer interface allows for the generic concept of channels to deal with

multiple logical channels for one physical interface. The integrated Endpoint block

supports eight traffic classes each having three traffic types: posted, non-posted, and

completion.

Channel Ready

When the integrated Endpoint block is ready to accept a packet into one of the buffers, it

asserts the appropriate channel ready signal(s). There is one channel ready signal per

traffic class, according to the type of packet (

LLKTXCHPOSTEDREADYN[7:0],

LLKTXCHNONPOSTEDREADYN[7:0], and LLKTXCHCOMPLETIONREADYN[7:0]). More than

one channel can be ready on any clock cycle.

Channel Select

The user application sets LLKTXCHTC[2:0] to select the traffic class and LLKTXCHFIFO[1:0] to

indicate in which TX FIFO the data is to be placed: posted (00), non-posted (01), or

completion (10).

LLKTXDSTRDYN is asserted when the selected channel has space available, and

LLKTXCHANSPACE reports the amount of free space. Pipelining causes a delay of one cycle

between a change in a channel select and an output based on a selected channel

(

LLKTXDSTRDYN or LLKTXCHANSPACE). Also, it takes four clock cycles to update

LLKTXCHANSPACE after a write transaction.

Transmit Framing

The user application uses the framing signals to indicate the start and end of frames as well

as the position of the header and digest (if present). The framing signals also indicate how

many 32-bit DWORDs are valid at the end of the header and the end of the frame.

The

LLKTXSOFN and LLKTXEOFN signals delineate the frame boundaries.

Figure 2-5: Transaction Layer Interface Transmit Timing Diagram Showing a 4 DW Header

CRMUSERCLK

LLKTXSOFN

LLKTXEOFN

LLKTXSRCRDYN

LLKTXDSTRDYN

LLKTXDATA

LLKTXENABLEN

UG197_c2_03_111906

H0 H1 H2 H3 P0 P1 P2 P3 P4 P5 P6 P7

00 00 00 00 00 11 00 00 1111

1 ... 28 29 30 ... 120

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