AMX DESIGN XPRESS V 1.5 - PROGRAMMER GUIDE User's Guide download pdf (Page 55)

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UG197 (v1.5) July 22, 2009

Registers

Message Signaled Interrupt (MSI) Capability Structure

Table 2-19 summarizes the MSI registers.

PCI Express Capability Structure

Table 2-20 summarizes the PCI Express Capability registers.

Table 2-19: MSI Registers

Management

Address (Hex)

MGMTADDR[10:0]

(1)

Read Only or

Read Write

22 Message Control; Next Pointer; Capability ID RW; RW; RO

23 Message Address RO

24 Message Upper Address RO

25 Reserved (16 bits); Message Data (16 bits) RO; RO

26 Mask Bits RO

27 Pending Bits RO

Notes:

1. The register names are listed as they are read on MGMTRDATA[31:0] or written to MGMTWDATA[31:0].

Table 2-20: PCI Express Capability Registers

Management

Address (Hex)

MGMTADDR[10:0]

(1)

Read Only or

Read Write

28 PCIe Capabilities Register; Next Cap Pointer; PCIe Cap ID RW; RW; RO

29 Device Capabilities RW

2A Device Status; Device Control RO; RO

2B Link Capabilities

(2)

2C Link Status

(2)

; Link Control RW; RO

2D Reserved N/A

2E Reserved N/A

2F Reserved N/A

30 Reserved N/A

Notes:

1. The register names are listed as they are read on MGMTRDATA[31:0] or written to MGMTWDATA[31:0].

2. Bit 20 of the Link Capabilities register (Data Link Layer Active Reporting Capable) and bit 13 of the Link Status register (Data Link

Layer Link Active) both have a correct value of 0 when read through the PCI Express serial link, but return a value of 1 when read

from the Management interface.

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