AMX DESIGN XPRESS V 1.5 - PROGRAMMER GUIDE User's Guide download pdf (Page 47)

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 47

UG197 (v1.5) July 22, 2009

Virtex-5 FPGA Integrated Endpoint Block Interface Descriptions

L0MACNEGOTIATEDLINKWIDTH[3:0]

Output core_clk Link width selected after negotiation,

as follows:

0001: One lane

0010:Two lanes

0100: Four lanes

1000: Eight lanes

L0MACLINKTRAINING

Output core_clk Indicates that link training is in

progress. Reset to logic 1. Goes Low

when the link reaches the L0 state at the

end of link training. If link training

fails, the signal is pulsed Low for one

clock cycle before the block reenters the

detect state.

L0LTSSMSTATE[3:0]

Output core_clk The state of the Link Training and

Status State Machine, encoded as

follows:

0000:Initial

0001: Detect

0010: Polling

0011:Configuration

0100:L0

0101: L0sTx

0110:L1

0111:L2

1000: Testmode Wait

1001: Loopback

1010: Hot Reset

1011: Disabled

1100: Recovery

1101:L0 to Recovery

1110: L0 to L0sTx

1111: L0 to L1/L2

Note: The encodings 1101, 1110, and

1111, corresponding to L0 transition

states, identify where the device is still

nominally in the L0 state but cannot

transmit data.

L0DLLVCSTATUS[7:0]

Output core_clk Indicates the flow control initialization

process for the corresponding VC is

complete. A 1 indicates the VC is

initialized.

Bit [0]: VC0 status

Bits [7:1]: Reserved

Table 2-16: Configuration and Status Ports (Continued)

Port Direction

Clock

Domain

Description

1 ... 46 47 48 ... 120

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