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4–2 Chapter 4: Parameter Settings for the Cyclone V Hard IP for PCI Express
System Settings
Cyclone V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
RX Buffer credit
allocation -
performance for
received requests
Minimum
Low
Balanced
High
Maximum
Determines the allocation of posted header credits, posted data credits,
non-posted header credits, completion header credits, and completion
data credits in the 6 KByte RX buffer. The 5 settings allow you to adjust
the credit allocation to optimize your system. The credit allocation for
the selected setting displays in the message pane.
Refer to Chapter 13, Flow Control, for more information about
optimizing performance. The Flow Control chapter explains how the RX
credit allocation and the Maximum payload size that you choose affect
the allocation of flow control credits. You can set the Maximum payload
size parameter in Table 4–2 on page 4–4.
■ Minimum–This setting configures the minimum PCIe specification
allowed for non-posted and posted request credits, leaving most of
the RX Buffer space for received completion header and data. Select
this option for variations where application logic generates many read
requests and only infrequently receives single requests from the PCIe
link.
■ Low– This setting configures a slightly larger amount of RX Buffer
space for non-posted and posted request credits, but still dedicates
most of the space for received completion header and data. Select
this option for variations where application logic generates many read
requests and infrequently receives small bursts of requests from the
PCIe link. This option is recommended for typical endpoint
applications where most of the PCIe traffic is generated by a DMA
engine that is located in the endpoint application layer logic.
■ Balanced–This setting allocates approximately half the RX Buffer
space to received requests and the other half of the RX Buffer space
to received completions. Select this option for applications where the
received requests and received completions are roughly equal.
■ High–This setting configures most of the RX Buffer space for
received requests and allocates a slightly larger than minimum
amount of space for received completions. Select this option where
most of the PCIe requests are generated by the other end of the PCIe
link and the local application layer logic only infrequently generates a
small burst of read requests. This option is recommended for typical
root port applications where most of the PCIe traffic is generated by
DMA engines located in the endpoints.
■ Maximum–This setting configures the minimum PCIe specification
allowed amount of completion space, leaving most of the RX Buffer
space for received requests. Select this option when most of the PCIe
requests are generated by the other end of the PCIe link and the local
application layer logic never or only infrequently generates single
read requests. This option is recommended for control and status
endpoint applications that don't generate any PCIe requests of their
own and only are the target of write and read requests from the root
complex.
Table 4–1. System Settings for PCI Express (Part 2 of 3)
Parameter Value Description
- User Guide 1
- Contents 3
- Chapter 7. IP Core Interfaces 4
- Chapter 9. Reset and Clocks 5
- Chapter 18. Debugging 8
- 1. Datasheet 9
- 1–2 Chapter 1: Datasheet 10
- Features 10
- Notes to Table 1–2: 11
- Release Information 12
- Device Family Support 12
- Configurations 12
- Debug Features 13
- IP Core Verification 14
- Recommended Speed Grades 15
- 1–8 Chapter 1: Datasheet 16
- Hard IP for PCI Express 17
- Qsys Design Flow 25
- Generating the Testbench 26
- Simulating the Example Design 27
- Modifying the Example Design 34
- Running Qsys 36
- Table 3–5 38
- On Chip r 40
- Direct BFM’s shared memory 47
- {*reconfig_xcvr_clk*} 50
- Compiling the Design 51
- Programming a Device 51
- System Settings 54
- Port Functions 55
- Error Reporting 57
- 31 19 18 17 16 15 14 58
- Power Management 59
- Legacy Interrupt 63
- Base Address Registers 66
- PCI Express/PCI Capabilities 67
- Header 68
- 6. IP Core Architecture 75
- Avalon-ST Interface 77
- RX Datapath 77
- TX Datapath 77
- Altera FPGA 77
- Clocks and Reset 78
- Interrupts 79
- Transaction Layer 79
- Protocol Layers 80
- Configuration Space 81
- Data Link Layer 81
- Figure 6–4. Data Link Layer 82
- Physical Layer 83
- Figure 6–5. Physical Layer 84
- Multi-Function Support 86
- PCI Express Avalon-MM Bridge 86
- Avalon-MM Bridge TLPs 88
- Figure 6–9. Poor Address Map 93
- RX Block 97
- Avalon-MM RX Master Block 97
- TX Block 98
- Interrupt Handler Block 98
- 7. IP Core Interfaces 99
- Note to Table 7–1: 100
- RX Port 102
- Avalon-ST RX Interface 104
- Note to Figure 7–8: 109
- Avalon-ST TX Interface 114
- Note to Table 7–4: 117
- ECRC Forwarding 122
- Clock Signals 122
- Reset Signals 123
- and the LTSSM L0 state 125
- ECC Error Signals 126
- Interrupts for Endpoints 126
- Interrupts for Root Ports 127
- Completion Side Band Signals 127
- Specification, Rev. 2.1 129
- D E F 0 1 2 3 132
- Notes to Table 7–12: 133
- LMI Signals 137
- LMI Read Operation 138
- LMI Write Operation 138
- Power Management Signals 139
- (Full-Featured Qsys) 141
- Completer-Only Single DWord 142
- RX Avalon-MM Master Signals 144
- Transceiver Reconfiguration 146
- Serial Interface Signals 146
- PIPE Interface Signals 150
- Test Signals 153
- Notes to Table 7–26: 154
- 8. Register Descriptions 155
- Note to Table 8–2: 156
- Note to Table 8–3: 157
- Note to Table 8–4: 157
- Note to Table 8–5: 157
- Note to Table 8–6: 158
- Note to Table 8–7: 158
- Note to Table 8–8: 159
- s and wait 162
- PCI Express Mailbox Registers 167
- Note to Table 8–30: 168
- Root Port TLP Data Registers 170
- Sending a TLP 173
- Receiving a Completion TLP 173
- Endpoints 174
- Avalon-MM Mailbox Registers 175
- Spec 2.1 176
- 9. Reset and Clocks 181
- Example Design 182
- 127 cycles 184
- 300 PPM 185
- Transceiver Clock Signals 186
- Supported Message Types 189
- Notes to Table 10–1: 191
- Receive Buffer Reordering 192
- Notes to Table 10–2: 193
- MSI Interrupts 195
- 11–2 Chapter 11: Interrupts 196
- Note to Figure 11–4: 197
- Legacy Interrupts 198
- Application Layer 199
- 11–6 Chapter 11: Interrupts 200
- MSI/MSI-X Support 201
- Qsys System 202
- 12. Optional Features 203
- ECRC on the RX Path 204
- ECRC on the TX Path 205
- 13. Flow Control 207
- 13–2 Chapter 13: Flow Control 208
- Throughput of Posted Writes 208
- Chapter 13: Flow Control 13–3 209
- 13–4 Chapter 13: Flow Control 210
- 14. Error Handling 211
- Physical Layer Errors 212
- Data Link Layer Errors 212
- Transaction Layer Errors 213
- s limit 214
- Note to Table 14–4: 215
- Figure 15–2 218
- Core User Guide 219
- 16. SDC Timing Constraints 221
- Endpoint Testbench 224
- Root Port Testbench 225
- Chaining DMA Design Examples 226
- Root Complex 227
- Chaining DMA 227
- Hard IP for 227
- PCI Express 227
- Note to Table 17–2: 232
- Note to Table 17–4: 233
- Test Driver Module 236
- DMA Write Cycles 237
- DMA Read Cycles 239
- Root Port Design Example 240
- Root Port 241
- Variation 241
- (variation_name.v) 241
- Root Port BFM 242
- BFM Memory Map 244
- Figure 17–6 248
- BFM Read and Write Procedures 250
- BFM Procedures and Functions 251
- BFM Configuration Procedures 256
- Shared Memory Constants 257
- 18. Debugging 271
- 18–2 Chapter 18: Debugging 272
- Link Training 272
- Chapter 18: Debugging 18–3 273
- 18–4 Chapter 18: Debugging 274
- Chapter 18: Debugging 18–5 275
- Setting Up Simulation 276
- Chapter 18: Debugging 18–7 277
- Use Third-Party PCIe Analyzer 278
- BIOS Enumeration Issues 278
- Notes to Table A–7: 280
- Chapter : A–3 281
- Notes to Table A–16: 282
- Additional Information 283
- Info–2 Revision History 284
- How to Contact Altera 285
- Typographic Conventions 286
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