AMX DESIGN XPRESS V 1.5 - PROGRAMMER GUIDE User's Guide download pdf (Page 86)

6–12 Chapter 6: IP Core Architecture

Multi-Function Support

Cyclone V Hard IP for PCI Express December 2013 Altera Corporation

User Guide

Multi-Function Support

The Cyclone V Hard IP for PCI Express supports up to eight functions for Endpoints.

You set up the each function under the Port Functions heading in the parameter

editor. You can configure Cyclone V devices to include both Native and Legacy

Endpoints. Each function replicates the Configuration Space Registers, including logic

for Tag Tracking and Error detection.

Because the Configuration Space is replicated for each function, some Configuration

Space Register settings may conflict. Arbitration logic resolves differences when

settings contain different values across multiple functions. The arbitration logic

implements the rules for resolving conflicts as specified in the PCI Express Base

Specification 2.1. Examples of settings that require arbitration include the following

features:

■ Link Control settings

■ Error detection and logging for non-function-specific errors

■ Error message collapsing

■ Maximum payload size (All functions use the largest specified maximum payload

setting.)

1 Altera strongly recommends that your software configure the Maximum payload size

(in the

Device Control

■ Interrupt message collapsing

You can access the Configuration Space Registers for the active function using the

LMI interface. In Root Port mode, you can also access the Configuration Space

Registers using a Configuration Type TLP. Refer to “Configuration Space Register

Content” on page 8–1 for more information about the Configuration Space Registers.

PCI Express Avalon-MM Bridge

In Qsys, the Cyclone V Hard IP for PCI Express is available with either an Avalon-ST

or an Avalon-MM interface to the Application Layer. When you select the Avalon-MM

Cyclone V Hard IP for PCI Express, an Avalon-MM bridge module connects the PCI

Express link to the interconnect fabric. The bridge facilitates the design of Root Ports

or Endpoints that include Qsys components.

The full-featured Avalon-MM bridge provides three possible Avalon-MM ports: a

bursting master, an optional bursting slave, and an optional non-bursting slave. The

Avalon-MM bridge comprises the following three modules:

■ TX Slave Module—This optional 64- or 128-bit bursting, Avalon-MM dynamic

addressing slave port propagates read and write requests of up to 4 KBytes in size

from the interconnect fabric to the PCI Express link. The bridge translates requests

from the interconnect fabric to PCI Express request packets.

■ RX Master Module—This 64- or 128-bit bursting Avalon-MM master port

propagates PCI Express requests, converting them to bursting read or write

requests to the interconnect fabric. If you select the Single dword variant, this is a

32-bit non-bursting master port.

1 ... 85 86 87 ... 288

AMX DESIGN XPRESS V 1.5 - PROGRAMMER GUIDE User's Guide Page 86

Comments to this Manuals

AMX DESIGN XPRESS V 1.5 - PROGRAMMER GUIDE User's Guide Page 86

Comments to this Manuals

Related products and manuals for TVs & monitors AMX DESIGN XPRESS V 1.5 - PROGRAMMER GUIDE