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Chapter 17: Testbench and Design Example 17–39
BFM Procedures and Functions
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
ebfm_display Verilog HDL Function
The
ebfm_display
procedure or function displays a message of the specified type to
the simulation standard output and also the log file if
ebfm_log_open
is called.
A message can be suppressed, simulation can be stopped or both based on the default
settings of the message type and the value of the bit mask when each of the
procedures listed below is called. You can call one or both of these procedures based
on what messages you want displayed and whether or not you want simulation to
stop for specific messages.
■ When
ebfm_log_set_suppressed_msg_mask
is called, the display of the message
might be suppressed based on the value of the bit mask.
■ When
ebfm_log_set_stop_on_msg_mask
is called, the simulation can be stopped
after the message is displayed, based on the value of the bit mask.
ebfm_log_stop_sim Verilog HDL Function
The
ebfm_log_stop_sim
procedure stops the simulation.
ebfm_log_set_suppressed_msg_mask Verilog HDL Function
The
ebfm_log_set_suppressed_msg_mask
procedure controls which message types
are suppressed.
Table 17–37. ebfm_display Procedure
Location altpcietb_bfm_driver_rp.v
Syntax
Verilog HDL: dummy_return:=ebfm_display(msg_type, message);
Argument
msg_type
Message type for the message. Should be one of the constants defined in Table 17–36 on
page 17–38.
message
The message string is limited to a maximum of 100 characters. Also, because Verilog HDL does
not allow variable length strings, this routine strips off leading characters of 8’h00 before
displaying the message.
Return
always 0
Applies only to the Verilog HDL routine.
Table 17–38. ebfm_log_stop_sim
Location altpcietb_bfm_driver_rp.v
Syntax Verilog VHDL:
return:=ebfm_log_stop_sim(success
);
Argument
success
When set to a 1, this process stops the simulation with a message indicating successful
completion. The message is prefixed with
SUCCESS
:.
Otherwise, this process stops the simulation with a message indicating unsuccessful
completion. The message is prefixed with
FAILURE
:.
Return Always 0 This value applies only to the Verilog HDL function.
Table 17–39. ebfm_log_set_suppressed_msg_mask
Location altpcietb_bfm_driver_rp.v
Syntax
bfm_log_set_suppressed_msg_mask (msg_mask)
Argument
msg_mask
This argument is
reg [EBFM_MSG_ERROR_CONTINUE: EBFM_MSG_DEBUG].
A 1 in a specific bit position of the
msg_mask
causes messages of the type corresponding to
the bit position to be suppressed.
- User Guide 1
- Contents 3
- Chapter 7. IP Core Interfaces 4
- Chapter 9. Reset and Clocks 5
- Chapter 18. Debugging 8
- 1. Datasheet 9
- 1–2 Chapter 1: Datasheet 10
- Features 10
- Notes to Table 1–2: 11
- Release Information 12
- Device Family Support 12
- Configurations 12
- Debug Features 13
- IP Core Verification 14
- Recommended Speed Grades 15
- 1–8 Chapter 1: Datasheet 16
- Hard IP for PCI Express 17
- Qsys Design Flow 25
- Generating the Testbench 26
- Simulating the Example Design 27
- Modifying the Example Design 34
- Running Qsys 36
- Table 3–5 38
- On Chip r 40
- Direct BFM’s shared memory 47
- {*reconfig_xcvr_clk*} 50
- Compiling the Design 51
- Programming a Device 51
- System Settings 54
- Port Functions 55
- Error Reporting 57
- 31 19 18 17 16 15 14 58
- Power Management 59
- Legacy Interrupt 63
- Base Address Registers 66
- PCI Express/PCI Capabilities 67
- Header 68
- 6. IP Core Architecture 75
- Avalon-ST Interface 77
- RX Datapath 77
- TX Datapath 77
- Altera FPGA 77
- Clocks and Reset 78
- Interrupts 79
- Transaction Layer 79
- Protocol Layers 80
- Configuration Space 81
- Data Link Layer 81
- Figure 6–4. Data Link Layer 82
- Physical Layer 83
- Figure 6–5. Physical Layer 84
- Multi-Function Support 86
- PCI Express Avalon-MM Bridge 86
- Avalon-MM Bridge TLPs 88
- Figure 6–9. Poor Address Map 93
- RX Block 97
- Avalon-MM RX Master Block 97
- TX Block 98
- Interrupt Handler Block 98
- 7. IP Core Interfaces 99
- Note to Table 7–1: 100
- RX Port 102
- Avalon-ST RX Interface 104
- Note to Figure 7–8: 109
- Avalon-ST TX Interface 114
- Note to Table 7–4: 117
- ECRC Forwarding 122
- Clock Signals 122
- Reset Signals 123
- and the LTSSM L0 state 125
- ECC Error Signals 126
- Interrupts for Endpoints 126
- Interrupts for Root Ports 127
- Completion Side Band Signals 127
- Specification, Rev. 2.1 129
- D E F 0 1 2 3 132
- Notes to Table 7–12: 133
- LMI Signals 137
- LMI Read Operation 138
- LMI Write Operation 138
- Power Management Signals 139
- (Full-Featured Qsys) 141
- Completer-Only Single DWord 142
- RX Avalon-MM Master Signals 144
- Transceiver Reconfiguration 146
- Serial Interface Signals 146
- PIPE Interface Signals 150
- Test Signals 153
- Notes to Table 7–26: 154
- 8. Register Descriptions 155
- Note to Table 8–2: 156
- Note to Table 8–3: 157
- Note to Table 8–4: 157
- Note to Table 8–5: 157
- Note to Table 8–6: 158
- Note to Table 8–7: 158
- Note to Table 8–8: 159
- s and wait 162
- PCI Express Mailbox Registers 167
- Note to Table 8–30: 168
- Root Port TLP Data Registers 170
- Sending a TLP 173
- Receiving a Completion TLP 173
- Endpoints 174
- Avalon-MM Mailbox Registers 175
- Spec 2.1 176
- 9. Reset and Clocks 181
- Example Design 182
- 127 cycles 184
- 300 PPM 185
- Transceiver Clock Signals 186
- Supported Message Types 189
- Notes to Table 10–1: 191
- Receive Buffer Reordering 192
- Notes to Table 10–2: 193
- MSI Interrupts 195
- 11–2 Chapter 11: Interrupts 196
- Note to Figure 11–4: 197
- Legacy Interrupts 198
- Application Layer 199
- 11–6 Chapter 11: Interrupts 200
- MSI/MSI-X Support 201
- Qsys System 202
- 12. Optional Features 203
- ECRC on the RX Path 204
- ECRC on the TX Path 205
- 13. Flow Control 207
- 13–2 Chapter 13: Flow Control 208
- Throughput of Posted Writes 208
- Chapter 13: Flow Control 13–3 209
- 13–4 Chapter 13: Flow Control 210
- 14. Error Handling 211
- Physical Layer Errors 212
- Data Link Layer Errors 212
- Transaction Layer Errors 213
- s limit 214
- Note to Table 14–4: 215
- Figure 15–2 218
- Core User Guide 219
- 16. SDC Timing Constraints 221
- Endpoint Testbench 224
- Root Port Testbench 225
- Chaining DMA Design Examples 226
- Root Complex 227
- Chaining DMA 227
- Hard IP for 227
- PCI Express 227
- Note to Table 17–2: 232
- Note to Table 17–4: 233
- Test Driver Module 236
- DMA Write Cycles 237
- DMA Read Cycles 239
- Root Port Design Example 240
- Root Port 241
- Variation 241
- (variation_name.v) 241
- Root Port BFM 242
- BFM Memory Map 244
- Figure 17–6 248
- BFM Read and Write Procedures 250
- BFM Procedures and Functions 251
- BFM Configuration Procedures 256
- Shared Memory Constants 257
- 18. Debugging 271
- 18–2 Chapter 18: Debugging 272
- Link Training 272
- Chapter 18: Debugging 18–3 273
- 18–4 Chapter 18: Debugging 274
- Chapter 18: Debugging 18–5 275
- Setting Up Simulation 276
- Chapter 18: Debugging 18–7 277
- Use Third-Party PCIe Analyzer 278
- BIOS Enumeration Issues 278
- Notes to Table A–7: 280
- Chapter : A–3 281
- Notes to Table A–16: 282
- Additional Information 283
- Info–2 Revision History 284
- How to Contact Altera 285
- Typographic Conventions 286
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