Chapter 2. Architecture and technical overview 33
Draft Document for Review May 28, 2009 1:59 pm 4405ch02 Architecture and technical overview.fm
Figure 2-6 Memory DIMM slots for FC 5620, FC 5622, and FC 7380
In addition to the quad placement rules, minimum memory required depends from the number
of processor-cores configured in the 570:
2 GB is the minimum memory required for a 2-core system
4 GB is the minimum memory required for a 4-core system
8 GB is the minimum memory required for an 8-core system
16 GB is the minimum memory required for a 16-core system
Every processor card in a 570 configuration requires a memory quad.
The maximum installable memory is 192 GB per any 570 drawer, thus a fully configured 570
supports up to 768 GB (48 GB per processor-core).
When configuring the memory in a 570, placing 2 memory features (8 DIMMs) on a single
processor card will provide the maximum available memory bandwidth. Adding the third
memory feature will provide additional memory capacity but will not increase memory
bandwidth. System performance that is dependent on memory bandwidth can be improved by
purchasing two smaller features per processor card as opposed to one large feature per
processor card. To achieve this, when placing an order, ensure the order has 2X memory
features for every processor card feature on the order.
2.4.3 Memory consideration for model migration from p5 570 to 570
A p5 570 (based on POWER5 or POWER5+ processor) can be migrated to a 570. Since the
570 supports only DDR2 memory, if the initial p5 570 server to migrate has DDR2 memory, it
can be migrated to the target 570 that requires FC 5621 processor card to accept it.
Additional memory can be also included in the model migration order.
In FC 5621 processor card, the memory controller interfaces to four memory buffer chips per
processor card with 8 memory slots available to be populated with available DDR2 memory
DIMMs migrated from the p5 570 server (see Figure 2-7 on page 34 for memory DIMM slots
reference).
J2B
J1B
J0B
J2D
J1D
J0D
J2A
J1A
J0A
J2C
J1C
J0C
POWER6
chip
L3 cache
Comments to this Manuals